FPGA Experts

[jmcoreymv]

I'm using a virtex 2 fpga and my input clock is only 12.5 MHz. I need both a 90 deg and 270 deg phase shifted clock to be generated internally and unfortunately I found out the DLL in the virtex is rated for a minimum input of 24 MHz to work correctly. I was able to bypass the software error by changing my 'listed' input frequency and output frequency to 25 mhz in order to keep a 1:1 ratio. I checked the output clocks and they seem to be fine and properly shifted. Is there anything I should be worried about?

 

[bobsmith1492]

Meh, if it randomly locks up, you know you're going too fast, right? By DLL, did you mean PLL, by the way? If so, sometimes they need external components (some C, maybe R) that depend on the frequency; that might be just for procs with a wider range of possible input frequencies (is it supposed to be fixed for that unit?) Anyway, if it does have these, you might check if they could be modified for a more stable circuitl; that might help prevent problems.

 

[jmcoreymv]

The datasheet refers to it as a DLL for delay locked loop. Apparently the CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV are all powered off the DLL which is speced for a minimum frequency of 24 mhz in the low-frequency mode. I can however use the CLKFX outputs which are rated down to 1 MHz, but they dont give the phase shifts I need easily.

 

[nd]

I would be worried if it's able to lock on your 12.5 MHz clock. Assuming those DLLs are like the DCMs in the Virtex 4, does it have a "locked" output you can monitor?

 

[jmcoreymv]

Originally posted by: nd
I would be worried if it's able to lock on your 12.5 MHz clock. Assuming those DLLs are like the DCMs in the Virtex 4, does it have a "locked" output you can monitor?

I just checked it. Apparently it wasn't 'locking' even though the clock outputs looked good. I decided its probably not a safe route to take.