Four Motherboard Questions - *please reply*

[LowLight76]

I'm running an Asus P4T533 mobo, P4 2.8GHz CPU with a single Samsung 256MB RIMM4200.

1. Are the two chips that make up the Intel 850E chipset capable of moving 32-bit chunks of data?

2. Since the P4 2.8GHz CPU is a 32-bit processor, and the FSB speed that connects the CPU to the Intel MCH (North Bridge) is 533MHz, does this allow for 2.1GB/s bandwidth between the CPU and the Intel MCH?

3. 32-bit RIMM4200 operates at 1066MHz, but does this mean there is a 1066MHz bus speed that connects the two 232-pin RIMM sockets to the Intel MCH North Bridge?

4. The USB ports on my motherboard connect directly to a USB2.0 controller chip. When people say USB2.0 has a maximum bandwidth of 480MB/s are they referring to the bandwidth between the USB ports and the USB controller chip? If so, then what is the bandwidth between the USB controller chip and the Intel ICH2 South Bridge?

 

[Peter]

1. The chipset interlink is narrow and fast, that question sort of misses the point. Bandwidth there is 266 MB/s.

2. The CPU front side bus is 64 bits wide, and the clock is quad pumped 133 MHz (not the same thing as 533 MHz!).

3. Right, it's an insanely fast SERIAL bus. That's why the technology is so difficult to handle.

4. That's megaBITS per second. Having an USB 2.0 controller on the PCI bus is not a good thing, since you won't get full USB 2.0 performance there - especially not on Intel 850 chipset where a chipset issue holds PCI bus throughput down to around 3/4 of what other chipsets can do. If you need USB 2.0, you want to choose a mainboard that uses a chipset with integrated USB 2.0.

regards, Peter

 

[LowLight76]

Thanks for responding to my post. In asking question two, I knew the FSB was 133MHz quad pumped, but I didn't realize it was 64-bits wide. I'm glad you pointed that out b/c up until right now I've been confused on how there could be 4.2GB/s bandwidth between the processor and the North Bridge, when I knew full well that the P4 was just a 32-bit processor. You surprised me with your answer to my question two. Just so I'm totally 100% clear, are you telling me that the bus speed between the RIMM4200 memory sockets and the North Bridge is literally 1066MHz? ...that it's truly capable of sending/receiving 32-bit chunks of data to/from the North Bridge 1,066,000,000 times a second? As for my last question, I should've used a lower case B; my bad. But even still, the data does move from my USB2.0 ports to the USB2.0 controller and then to the South Bridge. So even though it's not the ideal chipset configuration for USB2.0, what's the bandwidth between the USB2.0 controller and the South Bridge? I'm thinking that it probably shares 133MB/s with every other PCI device that runs to the South Bridge. Is this correct? Thanks again.

 

[AndyHui]

The Pentium 4, being a 32-bit processor, means that its General Purpose Registers are 32-bits wide. This has nothing to do with the width of the front side bus.

The RDRAM bus is not actually running at 1066MHz. It is running at 533MHz, double pumped.

USB is running on its own connection back to the ICH South Bridge and does not share any PCI bandwidth with other PCI devices.

 

[Peter]

Sorry no, Andy, there is no other way for an USB 2.0 controller to connect to an ICH2 but PCI. Yes LowLight, it's on the same PCI bus as everything else you add there.

regards, Peter

 

[AndyHui]

Yes, I know it's a PCI device, but it doesn't share the same bandwidth as the PCI slots unless it is physically sitting on the same bus.

Or at least, that is what I understand from the South Bridge diagrams. IDE, USB, integrated LAN (all PCI devices) each have their own PCI connection back to the ICH, that is not shared, in addition to the PCI slots (which do share a single connection back to the ICH).

Otherwise there would be no point to Hublink/V-Link/MuTIOL would there?

 

[Peter]

That's correct, and true for the devices INSIDE the south bridge. Of course this is the whole point in having a fast north-south connection with the PCI bus hanging out the south's butt.

However, ICH2's internal USB is 1.1, so if you want to have USB 2.0, it's going to be on the actual PCI bus ... in general, if you see a separate USB controller chip, it's on the actual PCI bus, sharing bandwidth with everything else PCI, onboard or on cards.

Unless you use that Epox board that combines i850E north with an ICH4. This combination is not validated by Intel, but carries the advantage of having USB 2.0 integrated.

regards, Peter

 

[AndyHui]

Ah yes...sorry. You are talking about ICH2. For some reason I was thinking of the other chipsets (along with ICH4) in general which have USB 2 integrated.

Remind me to minimise posting at the end of a long hard day.