Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[OriAr]

Intel probably shipped around a few million ICL chips, not much by Intel standards but not that far from AMD's mobile volume and might be about equal to it. For comparison Intel might have shipped about 100M+ KBL-R and WHL chips.

Tiger Lake should be in much higher volume than Ice Lake, might not be far from WHL volume.

 

[piokos]

Intel probably shipped around a few million ICL chips, not much by Intel standards but not that far from AMD's mobile volume and might be about equal to it. For comparison Intel might have shipped about 100M+ KBL-R and WHL chips.

Tiger Lake should be in much higher volume than Ice Lake, might not be far from WHL volume.

Based on how Apple launches usually look and that that ICL is in MacBook Air and Pro 13, they've probably shipped few million for Apple alone.

Tiger Lake is the only planned mobile architecture for 11th gen, so it'll replace both Ice Lake and Comet Lake.

 

[jpiniero]

Tiger Lake is the only planned mobile architecture for 11th gen, so it'll replace both Ice Lake and Comet Lake.

Nope. There's Rocket Lake.

 

[piokos]

Nope. There's Rocket Lake.

I honestly thought Rocket Lake U was cancelled and Intel will just keep selling Comet Lake. But it seems you're right.

Anyway, Tiger Lake is at least expected to exist in all segments: Y, U and H.
And it seems it'll go all the way to 8 cores, so I'm not sure how they'll position Rocket Lake. Just as cheaper alternative?

 

[OriAr]

Nope. There's Rocket Lake.

Rumor around the block is RKL-U is cancelled, don't know how reliable it is but the fact that TGL has vPro SKUs shows there might be some truth to this rumor.

 

[DisEnchantment]

https://twitter.com/x/status/1259823968569053184

Hmmm... Xe in to be fabbed by TSMC in 2021 from TW sources.

 

[RetroZombie]

And now, since OEMs started using Ice Lake U popular notebooks, it seems rather plausible that there are no problems with delivering them in large quantities.

I would agree if the intel 10th gen was all compromised of 10nm which isn't, difficulties in manufacturing or low volume, they could just kept the 6/8 core parts on 14nm. But no, they still release duals and quads parts on 14nm just to compensate the lack of 10nm.

 

[piokos]

Hmmm... Xe in to be fabbed by TSMC in 2021 from TW sources.

It explicitly says: GPU or FPGA. Which means Intel reserved some fab capacity and leak author isn't sure what will be manufactured (or maybe TSMC and Intel don't know as well).

I would agree if the intel 10th gen was all compromised of 10nm which isn't, difficulties in manufacturing or low volume, they could just kept the 6/8 core parts on 14nm. But no, they still release duals and quads parts on 14nm just to compensate the lack of 10nm.

Just to anchor this discussion and your ideas about "low volume". Intel's mobile CPU volume is larger than whole of AMD.

Yes, they make mobile chips on 2 nodes. You can't automatically infer that it's because they have manufacturing problems.
The switch is not something you can do overnight. A manager just can't come to work on Monday, decide 10nm is OK and tell people to make Ice Lake from now on.
These CPUs are made on separate production lines, using different lithography equipment. Intel is gradually replacing their 14nm capacity with 10nm capacity. It'll take time.

 

[DrMrLordX]

@DisEnchantment

I'm still expecting DG2 to be fabbed at TSMC. Whether or not that also includes Ponte Vecchio or similar . . . ?

Intel is already fabbing FPGAs on 10nm. I think?

 

[piokos]

Intel is already fabbing FPGAs on 10nm. I think?

At least since August 2019. But they expect an increase in demand from autonomous cars, so outsourcing (at least partly) makes absolute sense.

The obvious outcome is that Intel won't be able to make all the 10/7nm chips it wants to sell: CPU, GPU, networking, FPGA, storage.
Depending on how their node compares to competition, they'll choose the products that should be manufactured internally.

 

[jpiniero]

Rumor around the block is RKL-U is cancelled, don't know how reliable it is but the fact that TGL has vPro SKUs shows there might be some truth to this rumor.

I could see it being cancelled due to OEMs rejecting it because of the power consumption, like Cooper Lake. Like the server market, OEMs could continue to use Skylake or use AMD more.

 

[OriAr]

Intel booking some capacity at TSMC is not surprising at all, Intel always had 20% or so of their products manufactured by 3rd party fabs.
I personally think it's for Mobileye, they already work with TSMC and their current lineup uses N7, not that much of a stretch to think they will use N5 too.
Xe using N5 will really surprise me, considering PVC uses 7nm and apparently 7nm is going pretty well in Intel, no need to use N5 out of all processes.

 

[piokos]

Rumor around the block is RKL-U is cancelled, don't know how reliable it is but the fact that TGL has vPro SKUs shows there might be some truth to this rumor.

And beside vPro and covering all 3 main segments (Y, U, H), there were even some leaks with TGL NUCs.
It does seem like TGL will be a universal platform - covering all products they usually target with mobile SoCs.

Which absolutely doesn't mean Intel has enough 10nm to completely leave 14nm.
I also think they'll just keep making 8th and 10th gen to fill the low-end demand. Tried and tested, good enough.

Rocket Lake brings a lot of good stuff (PCIe4.0, TB4, Xe GPU, 2.5Gbps LAN, AVX-512), but none of that would be utilized in cheap laptops.

 

[DisEnchantment]

Samsung's P2 fab will be expanded to cover foundry business. With this expansion, Samsung's cutting edge fabs for foundry business in 2021 will consist of S3, S4, V1 and P2.

Samsung Electronics Expands its Foundry Capacity with A New Production Line in Pyeongtaek, Korea

New line will become core manufacturing base for 5G·HPC·AI solutions with 5nm EUV Samsung began construction this month for volume production in 2H 2021

news.samsung.com

Photos

Spoiler

 

[DisEnchantment]

TSMC to move 5nm Plus process to volume production in 4Q20

TSMC is expected to kick off volume production of chips manufactured on an enhanced version of its 5nm FinFET process, dubbed tentatively 5nm Plus, in the fourth quarter of 2020, according to sources familiar with the matter.

www.digitimes.com

https://twitter.com/x/status/1265944271221227521

N5P in Q4 2020 !
Question is volume production of what? Apple is using N5 for this year.

 

[Doug S]

TSMC to move 5nm Plus process to volume production in 4Q20

TSMC is expected to kick off volume production of chips manufactured on an enhanced version of its 5nm FinFET process, dubbed tentatively 5nm Plus, in the fourth quarter of 2020, according to sources familiar with the matter.

www.digitimes.com

https://twitter.com/x/status/1265944271221227521

N5P in Q4 2020 !
Question is volume production of what? Apple is using N5 for this year.

N5 "plus" is not the same as N5P. Or at least for N7, there was N7, N7 plus (used some EUV layers) and N7P (no EUV) which improved performance.

I don't think N7+ had any claimed performance benefits, it was perhaps cheaper to use EUV instead of multipatterning for a few layers (or maybe wasn't cheaper but they considered the learning of using EUV helpful for the N5 ramp)

So what's N5+ supposed to be? Probably a more refined process, but not much in the way of performance improvement beyond better yields - which their customers would like as it would mean it is cheaper.

An "improved" N5 with better performance would probably be called N5P if they follow the N7 example, and probably not come out until Q2 or so of next year (they time their releases to match Apple's needs since Apple is paying them for early access)

As for what would use N5+, anything that targets mass production next year would probably want to use it because if it improves yields they save money. So probably the SD875 or whatever the thing that uses A78 and X1 is called may use N5+ rather than N5?

 

[Hitman928]

N5 "plus" is not the same as N5P. Or at least for N7, there was N7, N7 plus (used some EUV layers) and N7P (no EUV) which improved performance.

I don't think N7+ had any claimed performance benefits, it was perhaps cheaper to use EUV instead of multipatterning for a few layers (or maybe wasn't cheaper but they considered the learning of using EUV helpful for the N5 ramp)

So what's N5+ supposed to be? Probably a more refined process, but not much in the way of performance improvement beyond better yields - which their customers would like as it would mean it is cheaper.

An "improved" N5 with better performance would probably be called N5P if they follow the N7 example, and probably not come out until Q2 or so of next year (they time their releases to match Apple's needs since Apple is paying them for early access)

As for what would use N5+, anything that targets mass production next year would probably want to use it because if it improves yields they save money. So probably the SD875 or whatever the thing that uses A78 and X1 is called may use N5+ rather than N5?

N7+ (EUV) offers in the range of 15 - 20% density improvement and 10% power savings versus N7. Second gen N7 DUV (N7P) doesn't offer any density improvement that I am aware of but can give you slightly higher frequencies at iso power or around the same 10% power savings at iso frequency.

 

[Doug S]

N7+ (EUV) offers in the range of 15 - 20% density improvement and 10% power savings versus N7. Second gen N7 DUV (N7P) doesn't offer any density improvement that I am aware of but can give you slightly higher frequencies at iso power or around the same 10% power savings at iso frequency.

I was going by memory, I guess I should have looked it up. If N5+ improves density then it will really result in some savings, though a lot of that probably had to do with the EUV layers so I'm not sure if an N5+ would be able to achieve comparable improvement.

Whichever the story TSMC is on a two year cadence so the next big improvement (3nm) doesn't arrive until 2022. And these days "big" improvements are only found with density, the improvements in frequency/power are much smaller.

 

[DisEnchantment]

https://www.samsungfoundry.com/foun...yOut=homepageLayout&menuIndex=0504&blogId=280

Samsung published today a Statement from Samsung Foundry negating rumours of delays for its 5/4nm process development.

Just thought this could fit here.

Reposting here to not derail the other discussion.
Coverage in most Taiwanese media about Samsung Foundry are a bit biased I would say. This includes Digitimes.
They have problems on their leading edge nodes for sure, but far from being a failure.
And when you see most of the slides from TSMC they conveniently remove memory to highlight their advantage vs Samsung. (Which is true but not completely)

Samsung makes a lot of money from its fabs. It is just that they are more weighted towards memory products. Samsung has the highest Wafer output of any semi company (IDM and foundry) as of now according to ICInsights.

With 3GAE Samsung is aiming at performance, they are not going for absolute density. Whether it shapes up to be a success or not remains to be seen but at least they have some test chips already.

https://www.icinsights.com/news/bulletins/Five-Semiconductor-Companies-Hold-53-Of-Global-Wafer-Capacity

As of December 2019, Samsung had the most installed wafer capacity with 2.9 million 200mm-equivalent wafers per month. That represented 15.0% of the world’s total capacity and about two-thirds of it was used for the fabrication of DRAM and NAND flash memory devices. Major construction projects underway include large new fabs at its sites in Hwaseong and Pyeongtaek, Korea, and in Xi’an, China.

 

[randomhero]

There is lots of info about tsmc 5nm,packaging tech etc. on anandtech. com.
Just a heads up.

Edit: Tsmc keeps impressing me.

 

[DisEnchantment]

Samsung 3GAE gutted and delayed, 3GAE could be behind 4LPE it looks like.
2019

Compared to 7nm technology, Samsung’s 3GAE process is designed to provide up to a 45 percent reduction in chip area with 50 percent lower power consumption or 35 percent higher performance. The GAA-based process node is expected to be widely adopted in next-generation applications, such as mobile, network, automotive, Artificial Intelligence (AI) and IoT.

2021


New 4LPP/5LPP/8LPA node has been introduced
From IEDM 2020,
On an A75 Core : 7LPP -> 4LPE : 23% speed improvement (actual), 7LPP -> 4LPP : 29% speed improvement (estimated)
On an A57 Core : 7LPP -> 4LPE : 33% efficiency improvement (actual), 7LPP -> 4LPP : 46% efficiency improvement (estimated)
Details behind paywall.

Samsung Details 5nm and 4nm; Adds 8LPA, 5LPP, and 4LPP Nodes; Readies 3nm GAA For Next Year

Samsung revealed more details of its 5LPE process technology which recently ramped, gave a roadmap status update along with new stop-gap nodes announcement.

fuse.wikichip.org

TSMC official figures, on paper
N7 -> N3 : 32% speed improvement
N7 -> N3 : 69% efficiency improvement

In 2H2022, 4LPP will be ~4% less perf than N3 and a very significant ~15% less efficient. Theoretical logic density probably 30 - 35% behind N3.
Density not so big a deal, HPC devices cannot extract as much density as advertised by TSMC. Certain NV devices using 8N have higher density than AMD's N7P devices.
Another setback for Samsung.

For NV in 2H2022, if they are moving from 8N -> 5LPP, the jump is insane. And nobody to compete with for wafers.
8LPU -> 5LPP : 27% speed improvement (estimated)
8LPU -> 5LPP : 45% efficiency improvement (estimated)

8LPA probably for automotive chips.

 

[DrMrLordX]

Samsung 3GAE gutted and delayed, 3GAE could be behind 4LPE it looks like.

Good catch. Not a great time to be dependent on Samsung. Looking at you, Qualcomm.

 

[NTMBK]

Good catch. Not a great time to be dependent on Samsung. Looking at you, Qualcomm.

Isn't their biggest customer Samsung, anyway?

 

[Ajay]

Good catch. Not a great time to be dependent on Samsung. Looking at you, Qualcomm.

OTOH, not a great time to be a TSMC client wrt wafer allocations.

 

[Ajay]

Samsung 3GAE gutted and delayed, 3GAE could be behind 4LPE it looks like.
2019

2021
View attachment 46533

New 4LPP/5LPP/8LPA node has been introduced
From IEDM 2020,
On an A75 Core : 7LPP -> 4LPE : 23% speed improvement (actual), 7LPP -> 4LPP : 29% speed improvement (estimated)
On an A57 Core : 7LPP -> 4LPE : 33% efficiency improvement (actual), 7LPP -> 4LPP : 46% efficiency improvement (estimated)
Details behind paywall.

Samsung Details 5nm and 4nm; Adds 8LPA, 5LPP, and 4LPP Nodes; Readies 3nm GAA For Next Year

Samsung revealed more details of its 5LPE process technology which recently ramped, gave a roadmap status update along with new stop-gap nodes announcement.

fuse.wikichip.org

TSMC official figures, on paper
N7 -> N3 : 32% speed improvement
N7 -> N3 : 69% efficiency improvement

In 2H2022, 4LPP will be ~4% less perf than N3 and a very significant ~15% less efficient. Theoretical logic density probably 30 - 35% behind N3.
Density not so big a deal, HPC devices cannot extract as much density as advertised by TSMC. Certain NV devices using 8N have higher density than AMD's N7P devices.
Another setback for Samsung.

For NV in 2H2022, if they are moving from 8N -> 5LPP, the jump is insane. And nobody to compete with for wafers.
8LPU -> 5LPP : 27% speed improvement (estimated)
8LPU -> 5LPP : 45% efficiency improvement (estimated)

8LPA probably for automotive chips.

Hmm, guess wikichip has a paywall now