Discussion Foundry Node advances (TSMC, Samsung Foundry)

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NeoLuxembourg

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Oct 10, 2013
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Since the density focus is on SRAM bitcells those will become denser until there is no room for improvements anymore. Then the focus will switch to whatever cells offer the most room for further improvements. "High performance cores" as a target always have been on the opposite end of the density spectrum so will never be a focus on the pursuit in increasing density.
This will be interessting as PHYa, SerDes and other IO elements will be multiple times the size of single cores!
 

moinmoin

Golden Member
Jun 1, 2017
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This will be interessting as PHYa, SerDes and other IO elements will be multiple times the size of single cores!
Yeah, uncore in general is already a huge part of the overall power and silicon space budget. Since its also the very part that affects memory access latency (the part AMD's Zen chips so far are worst at, and Intel so far avoided changing by sticking to monolithic ring based chips in the mass market) it will be really interesting how this area will develop in the coming years.
 
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oak8292

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Sep 14, 2016
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More capacity investment has been planned, but to enable the likes of AMD to make a proper dent in the marketplace, at least 60-80K wpm are needed for AMD alone. If AMD were to be in a leadership position in the CPU market, they are going to need 300K+ wpm. Intel for example has around 800K+ wpm
Lots of guesses and speculation on my part. I don't know anything.

In these discussions on wafer capacity the wafer size always needs to be specified. Intel has around 800K+ wpm of 200mm equivalent wafers per the latest report from IC Insights. TSMC is running about 2500 wpm in an equivalent basis. The last couple of 'nodes' TSMC has ramped ~250 wpm of 200mm equivalent per node 'pair', e.g. 20/16/12 or 10/7nm.


AMD will have a challenge in getting adequate wafers from TSMC to compete with Intel at 5nm. Apple and Huawei are the two leading customers providing 20+% and 14% of TSMC revenue, or about the equivalent of AMDs annual revenue. Everybody is not going to get wafers at the leading edge. A lot of, if not most of AMD's product is going to stay on 7nm.

A lot of Intel's product is also going to stay on 14nm for the next couple of years. When Moore's Law was in full swing Intel depreciated equipment over four years and half of the production was on the trailing edge, (mainly XEONs and PCH). Intel 10nm capacity is probably going to be pretty limited if they plan on moving to 7nm in two years. Way back two, three or four years ago Intel claimed they were going to move XEON forward onto leading edge, it will be interesting to see what happens with that plan.

Something has to give because everybody and every wafer can't be on the leading edge. Apple is at TSMC because they are big enough to have customers to fill trailing edge fabs and everything doesn't have to be depreciated in two to three years.
 

moinmoin

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Jun 1, 2017
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AMD will have a challenge in getting adequate wafers from TSMC to compete with Intel at 5nm.
AMD won't have a challenge because it is already conservative with its orders and only orders what it plans to sell for sure (see "strongest" backlog quarter for Rome). TSMC sells its capacity to those who pay accordingly, AMD can pay when it can sell and usually is later than Apple and Huawei in joining new nodes anyway.
 

DrMrLordX

Lifer
Apr 27, 2000
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Will be really interesting how Intel's new biannual node cadence turns out.
Badly?

Intel hasn't executed like that on node advancements in awhile:

32nm: 2010
22nm: 2012
14nm: 2014
10nm: 2017
7nm: Q4 2021, we think.

Note that I've omitted all the problems with 14nm and 10nm that prohibited full product launches on each node. 14nm lagged on desktop until 2015, and 10nm is still lagging. 7nm will only be part of a GPU in 2021. If they stay on their current course, we should expect Intel 5nm pipecleaner products in Q4 2024.
 

moinmoin

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Jun 1, 2017
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We'll see. Intel's weirdly confident pushing that timeline so my first guess is maybe they actually keep the cadence on time this time, but with much smaller changes and improvements between them. But history wise Intel should be two nodes past 10nm by now already if being on time ever mattered to them, so... *shrugs*
 

moinmoin

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Jun 1, 2017
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@DrMrLordX

Yeah, that's the excuse we hear for quite some time now. "Intel's continual troubles with 10nm? Don't matter since 7nm will be EUV which will be much easier!" I then like to point out that if Intel ever intended to stick with its previous cadence 7nm should have come out between 2018 and this year already, but it's announced only for Xe graphics chips in late 2021.

Anyway will be really interesting how Intel's new biannual node cadence turns out. Would be inane if they fail at the first couple steps of it already.
 

jpiniero

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Oct 1, 2010
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@DrMrLordX

Yeah, that's the excuse we hear for quite some time now. "Intel's continual troubles with 10nm? Don't matter since 7nm will be EUV which will be much easier!" I then like to point out that if Intel ever intended to stick with its previous cadence 7nm should have come out between 2018 and this year already, but it's announced only for Xe graphics chips in late 2021.

Anyway will be really interesting how Intel's new biannual node cadence turns out. Would be inane if they fail at the first couple steps of it already.
Intel pretty obviously delayed buying EUV equipment. Which I think was mostly to save money by delaying the purchases until they needed it after giving 10 nm a full cycle.
 

dmens

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Mar 18, 2005
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We'll see. Intel's weirdly confident pushing that timeline so my first guess is maybe they actually keep the cadence on time this time, but with much smaller changes and improvements between them. But history wise Intel should be two nodes past 10nm by now already if being on time ever mattered to them, so... *shrugs*
All the bloviation is to keep the stock price up.

7nm will only be part of a GPU in 2021.
Don't you mean TSMC's 7nm? ;)
 

dmens

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Mar 18, 2005
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That is one conspiracy. The other is that Ponte Vecchio will have 7nm and 10nm components from Intel's fabs.
FWIW, Intel use of TSMC for upcoming products is pretty much an open secret within the industry at this point. Hard to keep the lid on something like that especially when anyone with the ability to leave Intel is jumping ship. We all know which way the company is headed.
 

DrMrLordX

Lifer
Apr 27, 2000
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FWIW, Intel use of TSMC for upcoming products is pretty much an open secret within the industry at this point. Hard to keep the lid on something like that especially when anyone with the ability to leave Intel is jumping ship. We all know which way the company is headed.
Even Ponte Vecchio though? I thought they were looking at TSMC (or Samsung?) for DG2.
 

dmens

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Mar 18, 2005
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Even Ponte Vecchio though? I thought they were looking at TSMC (or Samsung?) for DG2.
Just consider the importance of HPC accelerators vs mid grade gaming graphics and decide which product Intel will insist is homebrew 7nm. Gotta fake it til you make it.
 

DisEnchantment

Senior member
Mar 3, 2017
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FWIW, Intel use of TSMC for upcoming products is pretty much an open secret within the industry at this point. Hard to keep the lid on something like that especially when anyone with the ability to leave Intel is jumping ship. We all know which way the company is headed.
I thought Samsung Foundry, considering Raja's Korean trip.

Funny oxymoron comment
"We cannot confirm any stories related to our customers," a Samsung Electronics official said.
 

LightningZ71

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Mar 10, 2017
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In reference to AMD being heavily on leading edge nodes, why is that important? Given that they have rather successfully demonstrated that a modular chiplet design can not only be mass produced, but also demonstrate both leading edge total performance AND turn a profit, they have surely paved the way to get the best of both worlds, volume from a leading edge more sufficient to meet their market needs by using only a small die with the critical elements and a mainstream node for larger, less performance sensitive portions of the package to make up the rest of their volume needs. Then, using a mature node for their mobile parts where the focus is on balanced performance and efficiency at lower volumes.

Their products are nowhere near as space and power constrained as the cell phone centric mobile SOCs are and don't require a leading edge more, especially given their competition's current dilemma.
 

DisEnchantment

Senior member
Mar 3, 2017
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In reference to AMD being heavily on leading edge nodes, why is that important? Given that they have rather successfully demonstrated that a modular chiplet design can not only be mass produced, but also demonstrate both leading edge total performance AND turn a profit, they have surely paved the way to get the best of both worlds, volume from a leading edge more sufficient to meet their market needs by using only a small die with the critical elements and a mainstream node for larger, less performance sensitive portions of the package to make up the rest of their volume needs. Then, using a mature node for their mobile parts where the focus is on balanced performance and efficiency at lower volumes.

Their products are nowhere near as space and power constrained as the cell phone centric mobile SOCs are and don't require a leading edge more, especially given their competition's current dilemma.
A bit strange here or maybe I did not get the context.
I am of the opinion that AMD being on a leading node is important. Applies to every design house out there (applies to Intel/NVIDIA/Apple and others). Lets take Renoir as an example.
  • Efficiency
    • Without 7nm, Renoir's success is not going to be anywhere close to what it is now. This is possible because of N7's efficiency advantage vs the competition.
  • Density
    • Density gains enable AMD to pack 8 Cores and 8 CUs in a very small package. Sure they could have made it bigger if it was on older node. But for applications which need absolute compute density, like GPUs (NVIDIA's Tesla, for example, are usually very close to the reticle limit), density is a necessity. There is always a case to be made for density.
  • Economics
    • Density gains from N7 ensures that Renoir being a much smaller chip can extract maximum usage from wafer allocation i.e. more chips per die.
But as is always the case in Engineering, there are always tradeoffs and factors to consider.
In this case being on a leading edge node will make sense if/when
  • Yields are high enough
  • Available capacity is good enough
  • Density/Efficiency gains are compelling enough to undertake the risks and investments in process migration
  • Manufacturing costs makes sense for the product in question
  • Innovations are constrained by current process
There is a reason AMD want to be on N5. Why they didn't do it sooner is probably because of reasons above. (Apple had different goals which makes them want to get to N5 sooner and they have different cost/manufacturing/design targets).
Additionally, AMD is not only competing against Intel. Then there are ARM upstarts, there is NVIDIA besides Intel. Probably if not because of renewed competition from AMD, x86 would be lagging behind ARM in server CPUs. Seen the like of Cavium taking potshots at Intel's lack of innovation. Then there would have been ARM desktop CPUs.

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