Discussion Foundry Node advances (TSMC, Samsung Foundry)

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Geranium

Member
Apr 22, 2020
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Here is one important thing to remember : On paper density vs real die density. Intel may have more density on paper but real die density is way more less than the competition.
TSMC 7NM :

Low Power - Kirin 980 - N7 -> 93MT/mm2
Kirin 990 5G - N7+ -> 90.9MT/mm2

High Power - AMD Ranoir - N7 -> 62.82MT/mm2
AMD Navi10 - N7 -> 41.03MT/mm2
AMD Vega20 - N7 -> 39.96MT/mm2

Intel 10nm :

Low Power - Intel Lakefield - 10nm/10nm+ -> 49.4 MT/mm2

High Power - ???

TSMC 10nm :

Low Power - Kirin 970 - 10FF -> 56.86MT/mm2
 

DisEnchantment

Senior member
Mar 3, 2017
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All those tables comparing the technical specs of each foundry processes with each other all miss one important detail, the resulting yield rate.
I don't think there is public data that says this process has a defect density of 0.x/mm2. This is something only the fab and their customers will know.
We just have to make guesses. Most of the official info is very vague (80% yield, big die yields are good, yields are as good as last gen ...etc, no die area given)
Unfortunately, it is very hard to quantify this and better to be left out even though it is one of the critical information in the overall picture.
Here is one important thing to remember : On paper density vs real die density. Intel may have more density on paper but real die density is way more less than the competition.
The official density listed in the tables is usually the SRAM density (also historically been this way) and it is actually correct. Since the chip has many other other things, resulting density is much lower. You can see most fabs announce process milestones by taping out SRAM first.

SerDes, analog blocks, PHYs, IVRs etc cannot scale anywhere close to what is possible with SRAM. So Desktop chips which have a lot of these have much lesser overall density. Mobile chips don't have as much of these things and therefore are much more dense.
Also the type of cells being used are different. e.g.
HD cells are 2x2 fins which trade off contact area for density vs HP cells which are 3x3 fins (Intel 10nm is 2x3 fins according to TechInsights). eLVT devices are optimized for high drive currents to improve signalling rate at the cost of efficiency and density.

So there is a myriad of densities possible with different devices and probably a meaningful way to compare is ... SRAM density. And historically also has always been this way.

Even if the Fabs are lying, people like TechInsights will cut the chip and put the dies under an STM and measure the transistors, so the numbers are not off. e.g. they cut the Exynos 990 to verify Samsung's 7LPP density claims
With a 27nm fin pitch, this disruptive innovation enables a smaller standard cell height of 268nm while maintaining high drive current with a 3/3-fin layout for both NMOS and PMOS transistors.
1588323412230.png

But of course they will not know the yield/defect density.

On a side note, GPUs have a long history of tackling defects at the design level and I read an article some time ago about how David Wang managed to handle the initial high defect density of TSMC's 28nm process using redundant circuitries where applicable.
 

RetroZombie

Senior member
Nov 5, 2019
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Just finished reading the seekingalpha article, and the author bases all of it on the intel slides that we know are full of lies and failed timelines of the achievements and many other incorrect information.
Complete trash, wasted time.
 

amrnuke

Senior member
Apr 24, 2019
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Just finished reading the seekingalpha article, and the author bases all of it on the intel slides that we know are full of lies and failed timelines of the achievements and many other incorrect information.
Complete trash, wasted time.
Just the name of the site implies trying to do something that will largely do the opposite (i.e. trying to find specific investments that reliably beat the market as a whole is a fool's errand and over time tends to lose you money due to costs of trading compared to simple index investing). That is, unless it's interesting to study it, which makes it a hobby rather than something useful.

So it makes sense that their "journalism" is of about the same utility. Interesting, but not practically useful.
 

maddie

Diamond Member
Jul 18, 2010
3,159
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Just the name of the site implies trying to do something that will largely do the opposite (i.e. trying to find specific investments that reliably beat the market as a whole is a fool's errand and over time tends to lose you money due to costs of trading compared to simple index investing). That is, unless it's interesting to study it, which makes it a hobby rather than something useful.

So it makes sense that their "journalism" is of about the same utility. Interesting, but not practically useful.
Damn, you've just invalidated an entire subset of investing.

By your argument, none here should have bought AMD when the 1st news of Zen started to leak.
 

Ajay

Diamond Member
Jan 8, 2001
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While TSMC's N3 won't be unusable by most any standards, I still have very deep concerns about the final performance numbers from N3 with respect to thermals and switching speed. Sticking with FinFET should at least insure that they will have a working product, as FinFET's are quite well understood. I am just not highly confident that they will be able to extract enough heat from them per unit time to accommodate the required switching speeds at that node to be performance competitive. Granted, there are significant hurdles for all of the competition at that node, so my concerns there may not be market relevant. It may also be true that, given the inherent density gains from going to such a tiny node, they can relax their density goals and still achieve the needed performance without taking too much of a hit to productivity, as I also think that chips won't be able to shrink too much and still be able to achieve the I/O density that is needed. In other words, you still need to route thousands of pins into the chip. At some point, you can't shrink the chip any more and still get all the pins connected to it in a manner that keeps individual pin signal integrity to a sufficient level.
So, you make this comment without providing any evidence to support your conclusions. TSMC, behind the scenes, has been innovating on process chemistry and materials (proprietary, so I don't know what they've done). The semiwiki article doesn't provide any significant details about TSMC 3N - mainly they speculate as such:

Now the situation gets fuzzier, Intel’s 7nm process is due to start ramping in 2021 with a 2.0x shrink. Samsung and TSMC are both due to begin 3nm risk starts in 2021. Assuming Intel hits their date, they may briefly have a production density advantage but Intel’s 14nm and 10nm process have both been several years late. With COVID 19 impacting the semiconductor industry in general and the US in particular, a 2021 production date for Intel may be even less likely.

Figure 6 compares 2021/2022 processes assuming that within plus or minus a quarter or two all three processes will be available, I believe this is a fair assumption. Intel has said their density will be 2.0x 10nm, TSMC on their 2020-Q1 conference call said 3nm will be 70% denser than 5nm so presumably 1.7x... [ed:figured 6 is just an estimate]

In the case of TSMC they are shrinking 1.7x off of a 5nm process that is a 1.84x shrink from 7nm and they are bumping against some physical limits. With them staying with a FinFET I don’t expect the CPP to be below 45nm for performance reasons and even with SDB they will have to have a very aggressive cell height reduction. By implementing a buried power rail (BPR) they can get to a 5-track cell, BPR is a new and difficult technology and then an M2P of 22nm is required. Frankly such a small M2P raises issues with lithography and line resistance and BPR is also aggressive so I think this process will be incredibly challenging but TSMC has an excellent track record of execution.
I would expect that the 3N PDK and resultant designs will need to burn more xtors to raise IPC so that drive currents can be kept down (increasing switching times). This is the trend anyway. Anyway, with TSMC's success of late, the certainly cannot afford another 20nm fiasco and I have a reasonable confidence on their success. They have been using a more interative approach to process development than Intel, and have seen great success in doing so. Are there risks? Yes. Could 3N underperform in real designs? Yes. Is it too early to predict doom and gloom of 3N? Yes.

Here is a PDF on BPR for those interested: http://www.freepatentsonline.com/20180374791.pdf. Annoyingly, the diagrams are rotated.
 

RetroZombie

Senior member
Nov 5, 2019
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Toms hardware worker (freelancer), so?

Read some of his tweets, there's just to much bias, and excessive pro intel posts, and when posting about others always negative tone:
Dare question TSMC's (inherited) process leadership... But what if TSMC is pushing FinFET beyond its limits at N3, like planar 20nm?

He might get special privileged info from intel, and what he will do with it, left all the others in the dust?

Not sure if you tried to put him in some upper level, still not amazed with his writing.
 

Gideon

Senior member
Nov 27, 2007
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Toms hardware worker (freelancer), so?

Read some of his tweets, there's just to much bias, and excessive pro intel posts, and when posting about others always negative tone:
Dare question TSMC's (inherited) process leadership... But what if TSMC is pushing FinFET beyond its limits at N3, like planar 20nm?
He has always done that. You should read what he has posted here earlier and how accurate that turned out to be. In September 2016 he wrote:
Alright. You know what, I will leave my usual skepticism about TSMC/Samsung behind for a while.

So products around the same time as Intel 10nm, maybe earlier 'cause they're talking about tape-out in Q2. Although it might still well be only AAPL in '17.

Now, normally, I wouldn't believe this 7nm 1 year after 10nm and better yields than expected BS, but you know what, besides your subjective Apple comments, you do give some interesting information from time to time. So it might be that here we see the first prove of the materialisation of TSMC's parallel process node R&D. It very well could be, after their horrible 28nm node (which, I remind people, since people tend for forget quickly, it took them 4 years to get a successor for 28nm out of the fabs: 28nm AMD GPU early '12, 14nm GPU in '16).

So if TSMC pulls this off, then instead of them horribly falling behind Intel, which now seems unlikely, they will keep status quo with Intel, 2 years or so behind. I did not expect that at all (doing so well at these nodes) considering how much Intel is struggling with these nodes.

Of course we don't yet know precise timings and feature(s) (sizes), and with every passing node this gets worse since Intel and TSMC employ completely opposite node philosophies.
Or what his predictions for Rocket-Lake are:
 

Doug S

Senior member
Feb 8, 2020
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Sure if one assumes Intel will go back to a two year cadence (when even they will not claim that going forward) AND get a 2x area increase with each node AND execute perfectly then they will eventually catch up to and later overtake TSMC who has "only" been targeting in the 1.7x to 1.8x density increase per node.

Perhaps the reason Intel has had so many problems at 10nm and no picnic with 14nm at first either, while TSMC has kept all their promises and deadlines since right at the same time Intel started to misfire is because TSMC has been less religious about maintaining a 2x per node increase?

If Intel gets 2x but at a three year cadence they will fall further behind. Even if they get a larger than 2x increase like the 2.4x increase they were originally shooting for with 10nm before reality forced them to back off at three years per node they would still fall further behind TSMC.
 

Ajay

Diamond Member
Jan 8, 2001
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Perhaps the reason Intel has had so many problems at 10nm and no picnic with 14nm at first either, while TSMC has kept all their promises and deadlines since right at the same time Intel started to misfire is because TSMC has been less religious about maintaining a 2x per node increase?
Yes, TSMC uses a more incremental development system that doesn't _seem_ tied to an artificial cadence.
 

lopri

Elite Member
Jul 27, 2002
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Wondering how this applies to Nvidia's reputed use of both TSMC and Samsung fabs for next gen products.
From what I have heard, NV will not have a gaming GPU based on N7 until next year. Maybe that has something to do with it.
 

amrnuke

Senior member
Apr 24, 2019
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Damn, you've just invalidated an entire subset of investing.

By your argument, none here should have bought AMD when the 1st news of Zen started to leak.
Seeking to beat the market is an admirable effort. Do you know of anyone who has consistently beaten the market, and then had his/her future efforts tracked, and kept on beating the market? Do you think that represents even a sizable minority of writers / analysts on SA?

There is a big difference between buying something based on leaks and getting lucky, and consistently beating the market. A corollary: if someone had purchased Intel when leaks of 10nm came out, would they have beaten VTSAX?
 

Atari2600

Golden Member
Nov 22, 2016
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How long will the (expense of) developing and migrating to smaller processes continue to be justified at this pace?
 

trexfromouterspace

Junior Member
Feb 17, 2020
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How long will the (expense of) developing and migrating to smaller processes continue to be justified at this pace?
That's a good question, and the short answer is "as long as there's demand". 3nm is going to be way more expensive than 5nm, which is already way more expensive than 7nm. Then you throw the ongoing pandemic in, and it's murky.

The bottom line is that the fab dumps a ton of money into researching these processes, which is funded by companies building their chips on the processes, which is funded by customers buying the chips. If customers won't buy enough chips at desired prices, then companies won't order fab capacity, so the fab won't invest as much.
 

moinmoin

Golden Member
Jun 1, 2017
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How long will the (expense of) developing and migrating to smaller processes continue to be justified at this pace?
As long as the market profit possible from using smaller processes is bigger than the expenses for it. And considering just how profitable the iPhone business has been for Apple, it has to be crashing down for new processes not to be worth the expenses anymore.
 

Doug S

Senior member
Feb 8, 2020
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Every node gets more expensive, and design costs go up with every node. That means that the "minimum" number of chips a foundry client needs to buy for it to make sense goes up.

That's not really relevant for smartphone SoCs though, their volumes are way above any such threshold. I saw somewhere that the design/mask cost for a 3nm SoC would be about 3/4 of a billion dollars, 3x the cost of a 7nm design. At Apple's volumes that's only about $3 per SoC though. Not sure how it works for Qualcomm since they have a lot of different products, but I wouldn't be surprised to see them quit chasing the latest and greatest with their midrange (7 series) line at some point.

Intel has lower volumes than TSMC on leading edge nodes but they make a lot more money per chip thanks to triple digit ASPs so they're going to be fine chasing smaller processes for the foreseeable future as well.
 

Ajay

Diamond Member
Jan 8, 2001
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Eh, feature size will bottom out in the not to distant future, IMHO. It's not like we are going to see gates that are 5 atoms wide. Everything is going to go 3D inorder to increase density - though I that no idea how to cool such devices.
 

Doug S

Senior member
Feb 8, 2020
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Eh, feature size will bottom out in the not to distant future, IMHO. It's not like we are going to see gates that are 5 atoms wide. Everything is going to go 3D inorder to increase density - though I that no idea how to cool such devices.
Feature size already has no relationship with "7nm" and so forth and hasn't for years. The only size that might get too small in atoms is fin width, which is one of the reasons why FinFETs only have one more generation in them before we have to go to something new like GAA or CFET.
 

Ajay

Diamond Member
Jan 8, 2001
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Feature size already has no relationship with "7nm" and so forth and hasn't for years. The only size that might get too small in atoms is fin width, which is one of the reasons why FinFETs only have one more generation in them before we have to go to something new like GAA or CFET.
And how think will those go? Technically, graphene can go to 1 atom width, but unlikely in practice. Physics, in the end, will have it's say - and it's is close to saying no more shrinking for you.
I don't know why you are talking about process node names.
 

moinmoin

Golden Member
Jun 1, 2017
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You'll note the focus is always on overall density. Even if some parts get close to the physical limit there will always be other parts that can still be made denser in some way.
 

Ajay

Diamond Member
Jan 8, 2001
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You'll note the focus is always on overall density. Even if some parts get close to the physical limit there will always be other parts that can still be made denser in some way.
Heat density and dark silicon would mean that, no, this isn’t going to change much. At least for high performance cores.
 

moinmoin

Golden Member
Jun 1, 2017
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Heat density and dark silicon would mean that, no, this isn’t going to change much. At least for high performance cores.
Density so far has been mainly measured for SRAM bitcells, nobody is talking about density for "high performance cores". Which is exactly my point. ;)

Since the density focus is on SRAM bitcells those will become denser until there is no room for improvements anymore. Then the focus will switch to whatever cells offer the most room for further improvements. "High performance cores" as a target always have been on the opposite end of the density spectrum so will never be a focus on the pursuit in increasing density.
 

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