One thing that I forgot to mention earlier.... anyone else notice their claiming the XP4 has 8TMU's/pipe?!
I'm sure Trident would greatly appreciate being informed about that, as their still under the evidently mistaken impression it's 4X2 with the pipelines having shared resources, and 8layer MT.

A FAR cry from ET's claims of a full 4X8 architecture.
Mildly irritating that ET still doesnt seem to understand what TileBasedRendering is, as they mistakenly claim the XP4 is a tiler. The XP4 uses heirarcical tiling and is an IMR. That's the third article I've read wherein they confuse heirarcical tiling with a full tiling renderer ala PowerVR.
I'm still wondering how they managed to get the Trident XP4 to regress so much in performance compared to Anand's much earlier tests with a slower board then ET had.