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AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

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Abwx said:
Vth is in the 0.15-0.5V range, the higher Vth transistors (because there are different kinds in a design) will dictate the minimum voltage, hence the values you re quoting.
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While I'm not qualified to really contribute to these process discussions, I'll offer the simple observation: My N2830 Bay Trail Atom laptop(s), have an idle VID of 0.330V. So that falls somewhere in that range. I was amazed when I saw that with CPU-Z, I didn't know modern CPUs could even function at such low voltages.
 
bjt2 said:
Indeed I said that they should use another packaging technology, MCM for instance. But this poses limits on pin speed and power drain. The advantage of an interposer is to have many connections with lower power... HyperTransport doesn't scale well beyond 6.4GT/s... Probabily this is true also with interposer... But you can stuff 1024 bit buses, instead of 16-128 bit buses... And with a lower power consumption per pin... I think that AMD does not want to lose this train...



I have heard many times this as an upper soft limit for power dissipation in silicon chips... As I said it's not set in stone, but intuitively there should be an upper limit to power dissipation, because the thermal conducibility is not infinity...
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Heatspreader conductivity is different to the huge current leakage/hostspots at smaller geometries.

Sent from HTC 10
(Opinions are own)
 
LTC8K6 said:
And a 6C12T 5820K is just $320 at Microcenter...
5930K is $500
8C16T 5960X is $900
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That is why i have said a 8C 16T ZEN that is close to 5960X in performance will be fine at $600, faster than any 6C 12T Broadwell and cheaper than 8C 16T Broadwell but at a nice fat high margin $600.

Intel could still hold the very high end of 1K and higher segment. AMD doesnt need to compete in that as well to create profits, selling $400-600 ZEN SKUs will make them loads of profits.

Remember, they currently have less than $120-150 ASPs for Desktop (AM3+) SKUs, with ZEN they could increase ASP to $200-250 easily.
 
Just on the mcm vs interposer. We already know AMD cares about LLC cache locality so it doesn't need heavy read/write from any core to any LLC so traditional organic MCM packaging is "fine".

Also those leaks originally from Fud i think which have so far been correct had the server APU with the zepplins on a MCM and a interposer also on the MCM that the GPU + HBM sat on.
 
AtenRa said:
They can compete on price and have higher margins than today
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That was the point of my post. I'm not sure why there was confusion.

Claiming that AMD will price their CPUs at the same price/performance as Intel is hyperbole. They need to regain marketshare and mindshare. Forcing themselves into a niche by offering the same pricing for a perceived lesser brand is an absurd strategy. In fact, it goes beyond offering equitable price/performance into overpricing because marketshare/mindshare matters.

It is clear that some are hoping AMD will be unstrategic and price themselves out of pressuring Intel's margins. The only way that will happen is if AMD is run by people who stand to gain from Intel's margins not being pressured.
 
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I think the most realistic situation is that AMD fills in the gaps on the price/performance curve of Intel's stack outside of the extreme edges. It's doubtful AMD will have anything equal to the 6950X or 6900K but if the highest clocked 8C/16T chips can punch somewhere near that class they could launch their flagship(s) between $600 and $1000, but I would personally be stunned to see anything over $750. With the 6850K sitting right at $600 and the 6800K at $400 a lower clocked 8C/16T chip makes a lot of sense in that range. It might give up some ST performance but could compensate with better MT numbers and/or an unlocked multiplier. 4C/8T models make sense in the $175-300 range and just need to stagger the Intel offerings. $250 might be the sweet spot if they can't clock up high enough to trade blows with the $300/275 6700(K) but can provide more throughput than the $200 4C/4T 6600K. I'd imagine the floor for Zen is going to be about $150~175 with Bristol Ridge APUs covering the budget range until Raven Ridge is ready but the i3s/Pentiums will continue to take their lunch outside of iGPU performance. Even then, that's a massive improvement for AMD's market position, assuming the leaks can be trusted and they hit these marks.
 
behrouz said:
i can't open it



Edit: my bad.I forgot to refresh page to see latest post.nvm
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I could visit it yesterday but now I cannot, either the Forum mods locked it or it's some bait and switch scheme as they appear to be asking me to contribute now to access the forums. Umm no thx.
 
The Stilt said:
Checked out the "Blenchmark". E5-2699 V3 will sustain 2.6GHz when all cores / threads are loaded, regardless if it is a AVX2 workload or not.

2.77a public build:

14C/28T @ 2.3GHz = 90.40s
18C/36T @ 2.3GHz = 77.53s

2.78 MSVC 2015 build (the AVX2 one I posted yesterday):

14C/28T @ 2.3GHz = 62.16s
18C/36T @ 2.3GHz = 53.04s

I wouldn't be so sure that the "AMD ES" result is made on Zeppelin at all.
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sorry this seems a bit OT, but I am trying to run tests with this for the benefit of this thread so bear with me.

The 2.78a public build in particular is giving me really odd behaviour on both Skylake and FM2+ . I get bouts of what appear like low CPU use in task manager (80-90%) , but not reflected in HWmonitor, which is an apparent problem in itself, but during this behaviour it also plays havoc with both platforms Power managment - both downclocking to 2.7-2.8Ghz during this time, even when I've locked everything to 3Ghz (i'm doing clk/clk tests here).

This is two completely indepenent win10 installs for each platform

did you notice this at all? Even on your build's it does it at the very start of render.
 
majord said:
but not reflected in HWmonitor
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Could you elaborate a bit?
The CPU usage probably won't stay constantly at 100%, however a generic application cannot override the hardware configuration you've specifically set (i.e throttle down the CPU clock). If it truly does reduce the CPU frequency, then you have configured the power management incorrectly to begin with, or the power limits are insufficient.

Also HWMonitor is outdated, I would highly recommend to use HWInfo instead.
 
Sorry, I am using Hwinfo64. that was a typo.

Ok so to elaborate. For the FM2+ /x4 845 system:

in Hwinfo all for threads (cores) are staying pegged @ 100% (Core #x usage column) , yet when you open task manager, overall CPU utilization is hovering around 80%. (I can't say i've seen this sort of discrepency before)

Frequency for each core is reported @ 2700Mhz in HWinfo, until CPU usage in Task manager returns to 100%, then the reported frequency returns to 3000Mhz - yes this is counter intuitive to any sort of throttling.

If I run anything else - Pov ray, cinebench, none of this occurs.

I have APM off, C6 off, CPB off. 65w TDP (Thought I don't believe manipulating this does anything on FM2+ Carrizo)


On the i3 6100 system, similar behavior is observed though it seems only Task manager reports a low frequency (along with the low CPU usage), not HWinfo.

Shall investigate deeper, but just thought i'd see if there was something obvious first up, 🙂 What ever is going on, on both platforms the public release is performing stupidly bad with the above behaviour occuring:

core i3 6100@3Ghz:

2.78 Stilt build AVX2 :19m:44s
2.78 Stilt build no AVX2: 21:59
2.78 public release: 28m:07s

X4 845@3Ghz :

2.78 Stilt build AVX2: 28:48
2.78 Public release: 53m 18s
 
Dresdenboy said:
The whole thread seems to be missing. From cached pages I could search the poster's posts and see all except for the ones in that "amd zen" thread.
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If it did get removed/deleted it might be hint that it had some truth in it..... hopefully not the "buggy" part...
 
Funny thing about the "on package bios", "which takes 30 minutes to reset".

I know as a fact that the bios on these systems is not located on chip, but on the motherboard as usual. It would be impossible to have the bios located inside the CPU, since different boards require different code depending on their configuration. The bios contains initialization code & firmwares for the external peripherals, such as storage, network, audio, etc controllers and in some cases programming parameters for the VRM controller. Not to mention that nowdays most of the ODMs have proprietary functions in their bioses (such as tuning features).

So unless AMD plans to pre-program the CPUs to work only in a specific board model, or alternatively the ODMs plan to bundle the CPUs with their boards... well, make your own conclusions.

Zeppelin uses a new AGESA core version, but the basic layout & functionality is still the same as on previous platforms. Most, if not all boards will be using Aptio V bios from AMI.

Zeppelin does have a tiny ROM "on die", however it doesn't store anything bios related and there certainly is no need ever to "reset" it.

Also the SMU stands for "System Management Unit", it is not the abbreviation for AMD's SMT implementation like the "source" claims it to be. SMU is the "master of the puppets" on recent GPU ASICs and APUs / SoCs since Trinity. You've seen me talking plenty about the SMU in the past.
At least for now the multithreading implementation goes by it's original abbreviation, SMT.
 
I don't even know why anyone would need to try to decipher such bunk. It's just so obvious.

Sent from HTC 10
(Opinions are own)
 
blublub said:
If it did get removed/deleted it might be hint that it had some truth in it..... hopefully not the "buggy" part...
Click to expand...


This is a good indication. Some months ago I wrote that AMD isn't honest to us about their failed 2016 target, it seems even worse than I thought. This is what they called on track, they lied
 
The Stilt said:
Funny thing about the "on package bios", "which takes 30 minutes to reset".

I know as a fact that the bios on these systems is not located on chip, but on the motherboard as usual. It would be impossible to have the bios located inside the CPU, since different boards require different code depending on their configuration. The bios contains initialization code & firmwares for the external peripherals, such as storage, network, audio, etc controllers and in some cases programming parameters for the VRM controller. Not to mention that nowdays most of the ODMs have proprietary functions in their bioses (such as tuning features).

So unless AMD plans to pre-program the CPUs to work only in a specific board model, or alternatively the ODMs plan to bundle the CPUs with their boards... well, make your own conclusions.

Zeppelin uses a new AGESA core version, but the basic layout & functionality is still the same as on previous platforms. Most, if not all boards will be using Aptio V bios from AMI.

Zeppelin does have a tiny ROM "on die", however it doesn't store anything bios related and there certainly is no need ever to "reset" it.

Also the SMU stands for "System Management Unit", it is not the abbreviation for AMD's SMT implementation like the "source" claims it to be. SMU is the "master of the puppets" on recent GPU ASICs and APUs / SoCs since Trinity. You've seen me talking plenty about the SMU in the past.
At least for now the multithreading implementation goes by it's original abbreviation, SMT.
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AMD may be testing Eng Samples of the CPUs, not platforms. Fottemberg have said previously that AMD made tape outs of Zen on both: TSMC 16 nm FF+ and GloFo 14 nm FinFET processes. Who knows what they are doing?

Overall I do agree with you that 90% of what he posted is BS. However, I would also not rule out "possibilites".
 
Glo. said:
AMD may be testing Eng Samples of the CPUs, not platforms. Fottemberg have said previously that AMD made tape outs of Zen on both: TSMC 16 nm FF+ and GloFo 14 nm FinFET processes. Overall I do agree with you that 90% of what he posted is BS.
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What difference would it make what they're testing?

Your last statement applies on Fottemberg as well, although the bs content might be slightly higher than that 🙄
 
Porting an extremely complex design such as Zeppelin to a completely different process, just for a single purpose makes very little sense no matter how you look at it. Not that I would complain if such swap would be made though.
 
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