First nehalem CPU-z screenshot

[Nemesis 1]

Nehalem will come in variants for servers, desktops, and notebooks. The processor for four-socket servers is codenamed Beckton, the chip for two-socket servers Gainstown, and the chip for single-socket desktops is Bloomfield

According to DailyTech, all models of the desktop chip Bloomfield will have three DDR3 channels. The quad core models will have 8 MB of shared L3 cache (Penryn has 12 MB of semi-shared L2 cache), and the high-end models will have a 130 W TDP, compared to 136 W for high-end Penryns[5]. Desktop Nehalem processors will use either Socket LGA715 (Socket H) (according to DailyTech's Kristopher Kubicki) or Socket LGA1160 (according to PC Watch). Kubicki has stated that either he or PC Watch could have old documents. Server processors will use the LGA1366 socket with support for registered DDR3[6].

Seven codenames have been associated with the Nehalem microarchitecture in a PC Watch article. These include two server processors, three desktop processors, and two mobile processors. The server processor, Beckton, will have 44 bits of physical memory address and 48 bits of virtual memory address.

A HKEPC article [7] states that Nehalem is Penryn with microarchitectural and power efficiency improvements, including better lower power states and leakage reduction. Nehalem will, compared to Penryn, have 1.1x to 1.25x the single-threaded performance, 1.2x to 2x the multithreaded performance, 30% lower power usage for the same performance, and higher performance for the same power usage. It also states that Nehalem will have a "turbo mode" that enables cores to run at faster speeds than the TDP rated speed. Due to its early release and market segment, Bloomfield will not have an integrated memory controller, but it will still have QuickPath Interconnect. Its corresponding Tylersburg chipset supports dual channel and triple channel RAM, and a maximum of 24 GB RAM. Tylersburg will also support Quad CrossFireX.

Codename Market Segment Process Cores (Threads) Cache Memory Controller Bus Interface GPU Core? TDP Socket Preliminary Release Timeframe
Nehalem-EX (Beckton)[7] MP server 45 nm 8 (16) 24 MB in the last level (L3 or L4) Quad channel FB-DIMM2 4x QuickPath No 90/105/130 W Socket-LS (LGA1567) Q4 2009
Nehalem-EP (Gainestown)[7] DP server 4 (8) 8 MB Triple channel 800/ 1066/ 1333 MHz DDR3 2x QuickPath 60/80/130 W Socket LGA1366 Q4 2008
Bloomfield[7] High-end desktop Dual and Triple channel 800/ 1066/ 1333/ 1600[8] MHz DDR3 1x 6.4 GT/s QuickPath [9] 130 W
1x 4.8 GT/s QuickPath [10]
Lynnfield[7] Mainstream desktop Dual channel DDR3 1 PCIe x16 or 2 PCIe x8, DMI x4/x2 95 W Socket LGA1160 Q1 2009
Clarksfield[7] Mainstream mobile 45/55 W Q2 2009
Havendale[7] Mainstream desktop 2 (4) 4 MB 1 PCIe x16, DMI x4/x2 Yes 75 W [11]
Auburndale[7] Mainstream mobile 35/45 W


Pretty hard to say with everybodt missing up the detais.

In the above we have 4 sockets mentioned. LGA715. LGA 1166 LGA 1366 LGA 1567(Beckton)

Everyone is confused with the caches on these things including me. Some are calling the 8mb's of L2 cache L3 cache . Thats because intel changed something and none have really fifured out what it is.

The way I see it is like this. L1 will be .5 Mb semi shared cache. L2 will become fully shared . Merom /Penryn L2 is semi shared cache. Server chips(beckton) will have L3 fully shared cache. And requirer socket LGA1567.

It all so confusing . Spring IDF will ans most questons.

 

[Foxery]

Huh... the L1-Data cache is smaller than mu Core2 Duo. 32kb -> 16kb. Seems unusual for a cache to ever go *down* in any new generation CPU. (Granted, the L2/L3 are larger)

RE: 2 threads per core -- Nehalem brings back the concept of HyperThreading ("HT") seen on the Pentium 4, and supposedly they've revised it to be more effective. Core2 chips skipped that feature altogether.

 

[JAG87]

Originally posted by: Foxery
Huh... the L1-Data cache is smaller than mu Core2 Duo. 32kb -> 16kb. Seems unusual for a cache to ever go *down* in any new generation CPU. (Granted, the L2/L3 are larger)

RE: 2 threads per core -- Nehalem brings back the concept of HyperThreading ("HT") seen on the Pentium 4, and supposedly they've revised it to be more effective. Core2 chips skipped that feature altogether.

its actually 32KB of L1 data cache. in the thread at XS about this, the author of cpu-z replied and said that cpu-z is reading the L1 data cache as well as the FSB incorrectly.

 

[Nemesis 1]

Were did you see . L1 16kb ?

Before I seen the screen over at XS yesterday . The last info I had was ,.5mb l1 cache.


Penrym logic transitors. 19 million .

Nehalem 30 million logic transitors. Seems like a big jump in Logic transitors. Unless some of those are L1 cache transitors which make more sense. and would also make l1 cache >32kb.

While you've been off dreaming of long-range WiFi, Intel's not forgotten about its Penryn / Nehalem architectures, and thanks to an uber-boring slideshow presentation, we now know more than ever about the forthcoming duo. As expected, there isn't much new on the oft detailed Penryn front, but the fresher Nehalem most certainly piqued our interest; while built on the same 45-nanometer technology as its predecessor, Nehalem is being hailed as "the most dramatic architecture shift since the introduction of the front-side bus in the Pentium Pro in 1996." Attempting to back up such bold claims came news that HyperThreading would be native to Nehalem, and it would "share data at the L1 and potentially, the L3 cache levels," allow eight-core CPUs to clock down to two / four, and boast scalability options to satisfy a wider market. Most intriguing, however, was the "optional high performance integrated graphics" that could reportedly be included on the same processor die, which could certainly prove interesting if crammed into, say, a UMPC. So if you're still not satisfied with the highlights, and don't get enough mundane PowerPoint action from your corporate employment, be sure to hit the read link when your friends aren't looking.

I believe a shared L1 cache would be larger not smaller.

http://www.pcper.com/article.php?aid=382

 

[lopri]

DMI isn't a new name for FSB? It's currently implemented on Intel platform for NB to SB connection, essentially being PCI-E x4 interface. (bandwidth-wise) DMI is very slow compared to FSB which already is at 6.4GB/s (400FSB). Quick searching for QuickPath @Wiki says Intel is targetting 24GB/s~32GB/s with QuickPath.

 

[lopri]

What I'm trying to ask is, be it QuickPath or HyperTransport, the IMC should have some sort of clock generator and dividers to receive data from memory.

Doing a crude math, we know that DDR2-800 has a theoretical max bandwidth of 12.8 GB/s so DDR3-1600 = 25.6 GB/s. So it means the QuickPath is already saturated by memory bandwidth in theory. Sounds like there will be no room to play with multipliers and dividers unless Intel decides to give us high multipliers.. or you'll need a uber motherboard and uber memory.. ?

Too early to tell, for sure.

 

[bunnyfubbles]

Originally posted by: MarcVenice
DDR3 prices have been predicted to come down really soon, once manufacturers start cranking out that stuff full throttle for OEM pc's, but right now OEM pc's come with ddr2 most of the time, so no real need yet. But ddr3 prices should become 'real' second half of this year.

Yeah, it should be cheaper because of higher density (how DDR2 is so much cheaper than DDR1 right now), however with the market flooded with so much super cheap DDR2 the surplus is going to have to sell off otherwise it'll keep the DDR3 artificially inflated even if there isn't a supply problem. The prices won't be pure robbery like they are now but they'll still be higher than DDR2.

 

[n7]

If only it was running @ a 133 MHz FSB, imagine the OCing potential :evil:

Of course, it's not; it'll be running at something a ton higher, making decent OCing nearly impossible.

 

[JackBurton]

WOW. I think I can wait to upgrade my machine. 2008 & 2009? I think my 2.2GHz Athlon XP can hold out...maybe.