On-chip passives are definitely NOT low-tolerance. As a matter a fact, it is common for caps, resistors, (and especially inductors) to have tolerances upwards of 10%. I'm not an expert in the actual manufactiruing but I know that the loose tolerances are a problem when designing analog circuits. Digital circuits on the other hand, I imagine are more resilient to process variations.Originally posted by: Jassi
I have been reading up on how chips are manufactured and I am stuck on one important step. How do they fabricate capacitors and resistors on the chip with such low tolerance levels. If anyone has a step by step guide, that would help a lot.
Thanks,
Jassi
Originally posted by: TuxDave
Now when we are talking about tolerance, are we talking about getting close to an absolute value or getting close matching. For high resolution A/D and D/A converters, it's never a wise decision to depend on an absolute value for passive devices. Yes, laser trimming is an option but it's also very costly. The better solution is to allow the circuit to tune itself using some self-calibrating circuitry.
Originally posted by: Jassi
I have been reading up on how chips are manufactured and I am stuck on one important step. How do they fabricate capacitors and resistors on the chip with such low tolerance levels. If anyone has a step by step guide, that would help a lot.
Thanks,
Jassi
Originally posted by: fliguy84
Originally posted by: Jassi
I have been reading up on how chips are manufactured and I am stuck on one important step. How do they fabricate capacitors and resistors on the chip with such low tolerance levels. If anyone has a step by step guide, that would help a lot.
Thanks,
Jassi
capacitors cant be fabricated on silicon. they need AREA to increase the capacitance. so that's why u see those bad-ass capacitors on power supplies
Originally posted by: SpecialK
Originally posted by: fliguy84
Originally posted by: Jassi
I have been reading up on how chips are manufactured and I am stuck on one important step. How do they fabricate capacitors and resistors on the chip with such low tolerance levels. If anyone has a step by step guide, that would help a lot.
Thanks,
Jassi
capacitors cant be fabricated on silicon. they need AREA to increase the capacitance. so that's why u see those bad-ass capacitors on power supplies
You can definitely have capacitors (and resistors and inductors) fabricated on silicon. We just talked about it a couple weeks ago in an integrated circuit design class I am taking this semester.
Very true, Q-factor is a huge problem for on-chip inductors; I took an RF microelectronics class this semester and we spent a week just on modelling and use of on-chip inductors. At frequencies above 2 GHz or so, the models are horrific because of all the loss mechanisms. What's worse, inductors have a self-resonant frequency above which the inductor starts looking like a capacitor!Originally posted by: TuxDave
Originally posted by: SpecialK
Originally posted by: fliguy84
Originally posted by: Jassi
I have been reading up on how chips are manufactured and I am stuck on one important step. How do they fabricate capacitors and resistors on the chip with such low tolerance levels. If anyone has a step by step guide, that would help a lot.
Thanks,
Jassi
capacitors cant be fabricated on silicon. they need AREA to increase the capacitance. so that's why u see those bad-ass capacitors on power supplies
You can definitely have capacitors (and resistors and inductors) fabricated on silicon. We just talked about it a couple weeks ago in an integrated circuit design class I am taking this semester.
Yeah, it's very possible to get capacitors on chip but if you're talking about 10pF capacitors, yeah, that'll kill lots and lots of space. Oh, and if you want relatively good tolerance and linearity on your capacitors, you can give up trying to use gate oxide caps and be stuck with lateral metal to metal caps. But that'll mean you'll be playing with at around 500 of fF and that's still a pretty big chunk of area.
On silicon inductors is another really bad story. The best we can do is make a spiral of metal with a tap in the middle and one on the outside. The problem with that is it will be a relatively low Q inductor.
Originally posted by: Mark R
It's done with 'laser trimming'. Essentially, the original resistors are made with a deliberately low value. Then, when the die is undergoing testing, the individual resistors are measured and bit-by-bit burnt out with a laser until the values are exactly right. However, this is a specialist process and is expensive, so is normally reserved for high-performance chips.