- Oct 19, 2004
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Hmmm, I googled about everything I could, but I have not been able to securely verify whether the Nocona core (90nm Xeon) has the pipeline depth of the Prescott (31) or the Northwood (20), and what the L1 latency is.
Anybody knows for sure?
Clearly the safer guess is Prescott pipeline and L1 cache since it's 90nm, had SSE3 and all that Prescott stuff, but one person claimed they kept a 20-stage pipleline and the short L1 latency. That wouldn't be impossible given it came later and could have more development put into it.
Anybody knows for sure?
Clearly the safer guess is Prescott pipeline and L1 cache since it's 90nm, had SSE3 and all that Prescott stuff, but one person claimed they kept a 20-stage pipleline and the short L1 latency. That wouldn't be impossible given it came later and could have more development put into it.
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