Effect of SoC designs for the next 5-10 years?

[GWestphal]

Haswell appears to be focusing and dramatically altering power consumption with some mobile parts as low as 8W. Is this power rejiggering going to be the most significant change we see to power consumption or some of the other changes be more significant?

What will be the effects (especially power consumption related) of these?

1) Broadwell MCM/MCP integrating the the PCH onto the CPU. (CPU/GPU/Chipset) in one package.

2)14nm and 10nm shrinks of Broadwell and Skylake/Skymont. Related question at what size does metal ion diffusion come into play? When a lead is only like 5 atoms wide, aren't we going to have to worry about the diffusion of the copper ions breaking the circuit or are these more stable then I am thinking.

3) Conversion to Graphene or carbon nanotubes vs silicon semi-conductors. I'm assuming this is what intel talks about when they say they have cool materials for when they stop using silicon in 2017.

4) Memristor tech, could it replace DRAM completely? Could this enable near zero power sleep modes?

5)Optical interconnects

In terms of other components, the MCM advent seems like it will free up a lot of space on motherboards. Are we just going to see motherboards shrink to one chip +RAM+ I/O (PCI Express, SATA, DisplayPort, Thunderbolt, USB, Ethernet, Audio). Or perhaps a 3-4 chip solution (CPU/GPU/Chipset + SSD/Controller+ DIMM + (WiFI/UWB/WUSB/BT) all in BGA format) plus a few thunderbolt/USB ports (which could do ethernet/display/peripheral/audio). That seems like it would be a really clean setup. All you need then is wireless power and you won't have any (visible) cords.

What about actual PSUs? ATX is pretty clunky, with the reduced power from all of the above, shouldn't we be able to make PSU tiny with only passive cooling for a computer that has no moving parts?

Regarding connectors, how have we put up with HUGE DIMMs and PCI/E connectors? It can't be that difficult to make smaller interfaces.

It seems like we're not that far off from seeing the workstation quality performance in a tablet type form factor.

 

[ericloewe]

First of all, tablets will not replace Workstations within 5-10 years, probably more. In 10 years a tablet may be as fast as a current workstation, but historically, if you need real work done (renders, medical stuff, simulations, CAD, etc.) you can always benefit from more horsepower. Your average workstation will be much more powerful, but the software it runs will also need (or at least benefit from) the faster hardware.

In the near future (Haswell/Broadwell), besides die shrinks, there's only architectural changes when it comes to power. Integrating the CPU's power supply on the chip allows Intel to tightly control the power received by its processors, allowing for more complex sleep schemes.

Integrating more functions that are currently off-chip will result in lower power consumption, at the very least because less power needs to be used to communicate with said functions.

As for memristors, I've been hearing about them for several years now and we don't seem to be any closer to a real life use.

 

[Insert_Nickname]

1) Broadwell MCM/MCP integrating the the PCH onto the CPU. (CPU/GPU/Chipset) in one package.

I thought the Haswell architecture only integrated the PCH on the ULV chips. Far as I heard the standard desktop and mobile ones would still use a traditional PCH. Or have I missed something...?

 

[GWestphal]

That may be true, I've just seen that they will at least be starting the process. I'd assume by Broadwell or Skylake that all SKUs will be MCM.

 

[Insert_Nickname]

That may be true, I've just seen that they will at least be starting the process. I'd assume by Broadwell or Skylake that all SKUs will be MCM.

Well, I would suspect that Broadwell will use the same LGA-1150 package as Haswell. On the desktop at least. You may be right on Skylake, we shall see...

 

[GWestphal]

Oh I missed this the first time around. Word on the street is that broadwell will usher in a new socket to accommodate the MCM layout and use of interposers and various 3D chip hootenany.