EETimes: Globalfoundries, TSMC square off in litho

Discussion in 'CPUs and Overclocking' started by Idontcare, Mar 2, 2011.

  1. Idontcare

    Idontcare Elite Member

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    There's actually a lot of tidbits in the 2-pg article if you hit the link, but I found the comments regarding the desire to insert EUV at 20nm at GloFo to be the most intriguing.
     
  2. Acanthus

    Acanthus Lifer

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    Just give me a frigging die shrink on graphics cards already.

    The graphics market has stagnated hard because of the shrink issues at TSMC and GF.
     
  3. AtenRa

    AtenRa Lifer

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    We will see an Intel like Tick-Tock product cycle with GPUs from now on because of the 2 year manufacturing process interval in TSMC and GloFo.

    Tock will be a new GPU Architecture (Lets say Fermi GF100 for example) with new lithography process (Double the Transistor Count of previous GPU and 50%+ more performance).

    Tick will be a revision on the same lithography and ~20% more performance (Like GF110 or AMD HD6900)
     
  4. khon

    khon Golden Member

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    The main reason they want to use EUV is actually pretty simple: Higher throughput, especially when you go to 16-nm and beyond.

    To do 20nm with DUV, you have to do double patterning, which means you're literally doing each layer twice (or at least the critical layers), thus cutting your throughput in half. If you go to 16nm, you will have to do triple-patterning, so your throughput is a 1/3rd. Adding to this problem, is the fact that as you increase the number of patterning steps for a single layer, you're also drastically decreasing your process margin, so your yield will take a hit.

    If you do EUV on the other hand, you can simple do a single exposure per layer, which is faster. Or at least it will be, once the technology reaches maturity.

    This is also why companies may switch to EUV later, even if they already reached a certain resolution with DUV.
     
    #4 khon, Mar 2, 2011
    Last edited: Mar 2, 2011
  5. Idontcare

    Idontcare Elite Member

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    Similar logic goes into determining the maximum practical number of metal levels to implement in the BEOL as it is a trade-off between production costs (cycle-time and yields) versus wiring density and capacitance.

    Having been on that side of the fence, one of the big drivers for EUV (its more a driver against anything that requires multi-pass patterning) at the foundries is the cost per maskset which is a function of the number of masks.

    If you are Intel and you are recovering the cost of a maskset across the span of tens of thousands of wafers it is easier to recoup the cost of an few extra masks required for double-patterning, but if you are GloFo or TSMC and you have customers that might be doing just 1000wfr runs for the lifetime of the product then it is a lot more difficult to economically justify adding four or five more masks to the maskset.

    Of course EUV masks are undoubtedly going to be substantially more expensive than DUV masks, just as 193nm masks are more expensive than 365nm masks, but presumably the difference is not going to be prohibitive.
     
  6. AtenRa

    AtenRa Lifer

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    I sure need to read more on manufacturing

    any good links ??
     
  7. AtenRa

    AtenRa Lifer

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    very nice, thx ;)
     
  8. DanielNenni

    DanielNenni Banned

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  9. AtenRa

    AtenRa Lifer

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