EE's or CPE's: VHDL Question

[jmcoreymv]

For a lab I have to design a 1-hot-counter, which goes through four states. The state variables are Y3-Y0.
I wrote the VHDL code and it seems to work fine under the condition that I clear first. The simulation doesnt work until the point in time where I bring the clear high.

entity mycount is
Port ( CLR,C1,C0,CLK : in std_logic;
Z1,Z0,UP,DN,MT : out std_logic;
Y3,Y2,Y1,Y0 : buffer std_logic);
end mycount;

architecture Behavioral of mycount is
begin
process(CLK,CLR)
begin
if(CLR='1') then
Y3<='0';
Y2<='0';
Y1<='0';
Y0<='1';
elsif (rising_edge(CLK)) then
Y3<=(Y2 AND NOT C1 AND C0) OR (Y0 AND C1 AND NOT C0) OR (Y3 AND (C1 XNOR C0));
Y2<=(Y1 AND NOT C1 AND C0) OR (Y3 AND C1 AND NOT C0) OR (Y2 AND (C1 XNOR C0));
Y1<=(Y0 AND NOT C1 AND C0) OR (Y2 AND C1 AND NOT C0) OR (Y1 AND (C1 XNOR C0));
Y0<=(Y3 AND NOT C1 AND C0) OR (Y1 AND C1 AND NOT C0) OR (Y0 AND (C1 XNOR C0));
end if;
Z1<= Y3 or Y2;
Z0<= Y3 or Y1;
UP<= NOT C1 AND C0;
DN<= C1 AND NOT C0;
MT<= C1 XNOR C0;
end process;
end Behavioral;

So what Im not quite sure how to do is set the initial state variables (to tell it to start in state 0001 for example). Whats the syntax in VHDL for that?

 

[Stealth1024]

What's a CPE? I think you should say CE (Computer Engineer). lol

I've spent way too much time writing VHDL code last quarter

I would guess that you need to define all of your signals and variables with some starting value. Otherwise you are using them on both sides of the assignment operator and they will start out undefined, which results in an undefined.

To set them initially say something like:

sigName: in std_logic := '0';

 

[Stealth1024]

this is also a good time to point out that using the signal assignment: <= will mean delta delay issues which may cause your output to be wrong. Generally don't use output signals on the right side of that assignment operator.

 

[Stealth1024]

Are you an EE or CE? Just curious...

I'm a 2nd year CE major at RIT (oh the fun!).

 

[dighn]

i'm not sure if you can directly set intial values on ports. maybe u need to define some intermediate variables

 

[RaynorWolfcastle]

I think you're complicating your life just define your states using a type statement and an attribute statement. Once that's done, the rest is just a matter of of applying a bunch o
if(state = Y1) then
state <= Y2;
elsif(state = Y2) then
state <= Y3;


etc...

I'm pretty sure that'll work

 

[jmcoreymv]

I would do it that way, but the lab specifically asked us to use this equation method of finding the set and hold 1 values for implementing D-flip flops. Im an EE btw. So "sigName: in std_logic := '0'; " is the way to set an initial value? Ill try that thanks.

 

[jmcoreymv]

Thanks guys, that worked!