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EE's need help bringing two digital signals into phase

R

rbhawcroft

Senior member
I have two signal busses, one is from a video source, and the other a usb source, so i cant control the timing of either, except that the video will always be on and pll locked, where as the usb wont necessarily always be on.

I need to synchronise the 4 bit 108Mhz USB based parallel bus with the 6 bit 108Mhz Video based parallel bus, before feeding them into a 10 bit wide serialiser for FO transmission.

Im not an engineer proper, so can someone please tell me exactly what components i need to impede the USB based bus so that it goes into synchronisation with the video bus? I have both busses on a accompanying 'rising edge clocked' 108Mhz clock signal.😕
 
What do you really need to do this for? What your asking seems like it could be pretty difficult. It?s possible to make a small delay circuit using feedback to delay one of the signals until it receives a rising edge from the other signal, but doing something like that at 108 MHz may be kinda difficult. You could try to use the same clock for both systems but again, good luck. I?m thinking that what you?re asking is more of a project then just something you throw together. If you do get it working then let us know, I?d be impressed.
 
are you an electrical engineer? somebody told me that you could do it with a Phase Locked Loop.

One idea i had was to latch it with the usb sourced clock, and output it on the video sourced clock or something like that.

the two signals: 13.5 Mhz for the video and 12Mhz for the USB are multiplexed using the same shift register multiplexers (8x and 9x to 108Mhz)

fortunately the chip which (x's) increases the clock frequency is separate from the shift register multiplexer chip. This chip is both the output latch fo the data and the clock signal for the serdes transceiver, so i was wondering about using the one clock and throwing away the usb generated clock, and using the 108Mhz clock derived from the 8x video PLL to latch out both the video data and the usb data, but it doesnt look very friendly at a waveform level, so i wanted to do it with a separate 'phase changer' to bring the usb based signal into phase with the video signal.
 
Yes I am an electrical engineer. First of all, why do you want to sync the two signals and do you know what kind of modulation the signals are using?
 
the reason for synchronising two independant signals would be so that the two busses that they are on could be fed into a single serdes transceiver before being transmitted over a propreitary optical network. The video comes from a ADC video decoder for SVHS to 16 bit YUV from a PC graphics card, and the USB comes from a USB cable from the same PC and will carry any audio and two way control data.

surely there is a way of getting the usb based data stream into sync with the video bus?

I dont know what modulation means, both the data busses come from the same mux IC, CMOS 3.3V DC multiplexer at 108Mbps and with a 108MHz clock in rising edge clocked and a second clcok with falling edge clocked.


I wanted a chip that would take the usb data in with the usb data clock and put it out on the video data clock. both clocks are 108Mhz, isnt there a simple way of doing this?

PLL chips as far as i can see can calculate the phase difference between the two clocks but dont modify the data signal to be inline with the second clock.
 
I dont quite understand your question, but here's what I'm seeing (and corect me if i'm wrong):

You have two signals, video at 13.5Mhz and USB at 12Mhz. THe video has 6bits of information, USB has 4 bits of information and you want to combine the two signal lines into a 10-bit serial line running at 108Mhz (which happens to be at 8x the freq. of video, and 9x the freq of usb clocks).

If the above is correct, then I have the answer for you, but it'll cost you $1,000. 🙂

Here's what you do.. get a PLL with a vco range that includes 108Mhz. Set the divider ratio to 8 and use your video clock as the ref. clock. Doing that will synthesize a 108Mhz clock signal and will be "locked" at that frequency. Now that you have that 108Mhz clock, there are several ways to multiplex the two buses.

First way is to use a micro-controller using that 108Mhz clock to sample the data lines. Of course this requires you to program the controller to get the timing correct. The advantage of using this method is that it requires very little extra components.

Another way is to use discrete components to implement that controller. You would have to feed the two data lines (and their corresponding clock signals) to a shift-register to latch the data.

Since you don't have the USB clock line on all the time, feed that 108Mhz into a binary counter that counts to 9, so you get a 12Mhz signal out.

Feed the 13.5M and 12M clock and their corresponding data lines to two different shift registers so it can latch the data. Because your running at 108Mhz, the two clocks will only synchronize every 108Mhz. For the video data, that would mean you will need a 48-bit shift register (8x13.5Mhz at 6-bits) and for the USB data, you will need a 36-bit shift register. I'm not sure if they have such large registers, but you can cascade a few together to meet those requirements. After all the data bits are in the register, you can simply read them off.

Also, there will be a delay of 1/108Mhz due to the fact that your shifting data into the register and not reading them until the end of every 108Mhz cycle.
 
ok.

i have a usb cable, and a video cable.

the video is ADC'd to a 13.5Mbps signal over a 16bit parallel bus. the USB is a 12Mbps differential '2 bit' bus. I PLL extract a clock from the USB. the video has a clock.

i can't control the phase of either up to now relative to eachother.

i need to get them both onto a bus that can be multiplexed into a single data stream for FO transmission. they can both be multiplexed to 108Mhz. I figured i could somehow sync their two busses.


so i can get an mcu that will take the video 108Mhz clock and use that to output the data from the usb derived data bus? and it does this resynchronisation via internal circuitry? basically the data is clocked in on the usb mux clock at 108MHz and clocked out on the videos 108MHz clock?


i dont understand what you said about the 48 bit and 36 bit shift registers, sorry.

what would make this design easy is if i can get a chip that will accept a parallel bus in one side with the usb phased clock and put it out with the video syncronised video clock. the delay time would be variable but on average only 180 degrees. cant you do that with some kind of latching ic? which latches with one clock and emits with another? so:

data in + its clock -> ic -> same data out + on output/ video clock
 
Now that I thought about it a little more, multiplexing the two data lines with different clocks into one serial line at 108Mhz isn't going to be easy. Even if there's an IC that can do this, you will still have to build the circuitry to stabilize the clocks and that requires a PLL. Why do you need it on one fiber optic line? Why not just put it on two strands? Or use software to multiplex the two datas and send it out to the transceiver for the fiber optic line. You don't want to implement a hardware circuit that can be done using software.
 
i want it all on one fibre so that i only use one transceiver they are 60usd.

in terms of software, i was going to use some kind of mcu and dsp in a later rendition, but its my start-up and i dont have the money to get someone to write a lot of software.

its for a home optical network that will compete with wifi, so i need to keep costs down.

the PLL i looked at gave me a difference signal, i thought there was a second component that used the difference signal to bring forward a rising edge and bring forward a falling edge, making your signal into pahse with the other clock, isnt this how PLL works?

One option is I use a USB transceiver to capture the usb signal from a cable, and find one that clocks the transceived signal out on a 12MHz refrence clock that I derive from the video 108MHz. Another option is risking clocking the 108Mhz USB signal out with the Video 108MHz clock, however, it doesnt look nice at the timing level.

I really thought there would be a way of getting data external to a board onto the said board's clock phase.
Cant you get a chip that captures the data in some way on one side and outputs in with a rephased clock on the other side?

How could you use software to multiplex the two data signals, using protocoling? How much would that software cost to write up because i could write the protocols? I would need a dsp or sth that would accept a 12MHz two wire USB signal, and a 13.5MHz 16bit parallel bus for the video.
 
I think you got the concept of PLLs mixed up. The purpose of a PLL is to synthesize a frequency much higher than a given reference frequency. If you have a reference clock of lets say 10Mhz, your output frequency will be multiples of 10Mhz. And yes, the output can be differential, or single ended. The purpose of a PLL is to "lock" in the output frequency using feedback. Without that feedback control, a voltage-controlled oscillator would drift away from the desired frequency, thus, the feedback stabilizes the loop and prevents the VCO from drifting away. It can also be used to recover the clock signals from a digital line.

Anyways, I think what your asking about an IC that can take a clock and data input and spit out a different clock with same data input doesn't exist. The reason is that the video signal requires a bandwidth of 13.5Mhz, while your trying to squeeze that into a bandwidth of 12Mhz.

You can go from 12Mhz to 13.5Mhz though, but during that extra 1.5Mhz period, there would be zero data.

What I would do is get a good data acquisition device from a company like National Instruments and feed your video and usb signals into there. Then you can write your program in C/C++ to compose the single data stream from the two and send it out at 108Mhz through the data acquisition device. However, this would only work during the prototype stages of your design. In your final stage of design, you would need to replace that data acquisition/computer with physical circuitry, and that's where it will be become expensive (unless you design it yourself).
 
the chip i wanted is a chip that will take the 108MHz usb based signal in on the usb based signal clock, and output it on the video based clock, both at 108MHz. Thereby ensuring that the video parallel bus at 108MHz and the USB parallel bus at 108MHz are synchronised with repect to their rising edges ie they are essentially two halves of a single data bus.

ill have a look at the ic you suggested, thanks.
 
Sorry I couldn't help you much, I'm still trying to see what your doing.. maybe if you can post a timing diagram, or some kind of schematic of what you want to , I'll understand clearer.
 
ok
link

i did a quick circuit board gif. its all on therethe problem is getting two signals coming from off the board into pahse with eachother for transmission serially.
 
right, item 13 on the gif is what i wanted a chip that will accept the usb bus on one side and output the same data on the otherside into the serdes ic, but having rbrought the said data into phase with the video bus which is also going into th smae serdes ic.

the big problem is that the two busses 11 and 12 are not in phase unless i can link them together.

alternatively if i take the video clock for 11, which is emitted but the pll at 8 then i can divide this by 9 to get a 12MHz signal which can be used hopefully to clock the data out at 4, and then after this data has been multiplexed then it will be in synch hopefully on bus 12 with the video on bus 11

or i can use the pll at 8 to clock the data out of both 7 and 9, which would make them in sync, but ill have to check this further, and im not sure it would work.
 
Ok, I see the problem now 🙂

Are the two 108Mhz phases different everytime you turn the thing on? Or is there a constant phase difference? If its constant, how about feeding it through a few inverters (with external capacitors) until the phases align up? The inverters can provide a delay to line up the phases.

If the phase differences is random everytime you turn on the circuit, then you can try an AND gate and two latches. The output of the AND gate goes to 1 when the two 108Mhz signals are 1. That output gets fed into two latches (d-flip-flop or something similar) and each latch samples the data. The only problem with this approach is that at worse case, one of the 108Mhz is rising and the other is falling at the same time. Then you would have a problem...
 
the phase of the video is dependant on the analog frame sync signals of the svhs siganl, and the usb signal is dependant on the host clock alignment, so yes they are random.

ill have to look into the random phase difference solution you suggested, because im not an engineer, so ill have to find out exactly what you mean.

thanks ill reply next week then, thanks.
🙂
 
hi blah i think i have pretty muched solved it. i looked again at the data sheets for the serialiser and mux pll. Basically because its the same chip pair for both signals im goinmg to use the 108MHz clock from the video setup to clock the data out of the usb serialiser.

ill check properly when i get a engineer to finalise the design, however if you wanted to read through the data sheet to see if the design looks like it would work i could do a barter deal with you either for audio cables now, or a discount on some home optical networking hardware subject to it coming out successfully, what do you say?

all thats left now is a clock-extract for the incoming usb signal, and the mcu for programmig the video registers. which brings me to the compatibility issue. i am doing a pal version, but i guess you are NTSC-M in US so youd have do an EEPROM but i could supply the code.
 
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