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http://www.eetimes.com/electronics-...edicted-to-hit-big-bump-at-14-nm?pageNumber=0
A lot of great points made in the article.
The part about multi patterning reducing xtor performance (due to relaxed design rules) really jumped out at me. Apparently "relaxed design rules" involves bigger xtors/features, among other things, at any give node.
So where does Intel go from here?
If lithography becomes more expensive (and even begins to affect performance negatively), I would assume the company's increased emphasis on xtor design and material science becomes that much more important than it was in the past.
But then I begin to wonder how much gain could Intel get from EUV (when finally in production) on top of the strong gains the company is making with xtor design and material science?
Do we get to the point where a device patterned with EUV actually results in a respectable performance increase compared to an identical device quad patterned on 193nm immersion?
IEDM: Moore’s Law seen hitting big bump at 14 nm
Rick Merritt
12/11/2012 12:01 AM EST
SAN FRANCISCO – Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase—and still carry a hefty cost premium--due to the lack of next-generation lithography needed to make them efficiently, according to experts speaking at the International Electron Devices Meeting (IEDM) here on Monday (Dec. 10).
Chip makers must choose lithography options now for 14-nm node, two generation away from the 28-nm node in wide production for today’s smallest devices. But it will not be until 2014 that extreme ultraviolet (EUV) lithography tools will be available for limited commercial use, said Luc van den Hove, chief executive of the IMEC research center in Belgium, speaking to EE Times after a keynote talk here.
The cost of 14-nm wafers made with today’s 193-nm immersion lithography systems will be more than 90 percent greater than the cost of today’s 28-nm wafers. EUV would shave that increase to just under 60 percent, van den Hove estimated in his talk (see chart below).
The cost comes from the need to make as many as three exposures with today’s systems compared to just one with EUV. “The triple patterning is too complex so you will have to relax design rules or the chips will not yield,” said Kurt Ronse, an IMEC lithography specialist.
As a result, 14-nm chips likely will deliver about 15 to 20 percent performance boosts over the prior generation, rather than the typical 30 percent boost, estimated Ronse.
“It is likely some design rules at 14 nm will have to be relaxed somewhat,” said van den Hove in his keynote. “I believe the time to decide lithography options for 14 nm is basically now, and its clear EUV is not ready for the challenge,” he added, in response to a question.
“There is a tremendous effort to solve the [EUV] problems,” said van den Hove. “We believe the problems are not fundamental, they are engineering but it will require time."
Test driving EUV
Earlier this year, an Intel executive said the company believes it could make chips economically even down to 10-nm design rules without EUV, using quad patterning. Intel is believed to generally have higher costs of manufacturing than the rest of the industry, due to the relatively high price for its processors.
Intel, Samsung and TSMC have separately invested billions of dollars this year in ASML which is making the EUV systems. EUV requires a more powerful light source now in development at Cymer, which ASML acquired this year.
With the existing weak light source, today’s EUV systems pattern less than 20 wafers an hour. Chip makers need systems that can pattern more than 100 wafers/hour, said Ronse.
Chip makers will need to employ new materials or device types at each major node to continue Moore's Law scaling, according to researchers.
A lot of great points made in the article.
The part about multi patterning reducing xtor performance (due to relaxed design rules) really jumped out at me. Apparently "relaxed design rules" involves bigger xtors/features, among other things, at any give node.
So where does Intel go from here?
If lithography becomes more expensive (and even begins to affect performance negatively), I would assume the company's increased emphasis on xtor design and material science becomes that much more important than it was in the past.
But then I begin to wonder how much gain could Intel get from EUV (when finally in production) on top of the strong gains the company is making with xtor design and material science?
Do we get to the point where a device patterned with EUV actually results in a respectable performance increase compared to an identical device quad patterned on 193nm immersion?
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