EE Times: Moore's Law predicted to hit a speed bump

cbn

Lifer
Mar 27, 2009
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http://www.eetimes.com/electronics-...edicted-to-hit-big-bump-at-14-nm?pageNumber=0

IEDM: Moore’s Law seen hitting big bump at 14 nm
Rick Merritt
12/11/2012 12:01 AM EST

SAN FRANCISCO – Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase—and still carry a hefty cost premium--due to the lack of next-generation lithography needed to make them efficiently, according to experts speaking at the International Electron Devices Meeting (IEDM) here on Monday (Dec. 10).

Chip makers must choose lithography options now for 14-nm node, two generation away from the 28-nm node in wide production for today’s smallest devices. But it will not be until 2014 that extreme ultraviolet (EUV) lithography tools will be available for limited commercial use, said Luc van den Hove, chief executive of the IMEC research center in Belgium, speaking to EE Times after a keynote talk here.

The cost of 14-nm wafers made with today’s 193-nm immersion lithography systems will be more than 90 percent greater than the cost of today’s 28-nm wafers. EUV would shave that increase to just under 60 percent, van den Hove estimated in his talk (see chart below).

Costs.jpg


The cost comes from the need to make as many as three exposures with today’s systems compared to just one with EUV. “The triple patterning is too complex so you will have to relax design rules or the chips will not yield,” said Kurt Ronse, an IMEC lithography specialist.

As a result, 14-nm chips likely will deliver about 15 to 20 percent performance boosts over the prior generation, rather than the typical 30 percent boost, estimated Ronse.

“It is likely some design rules at 14 nm will have to be relaxed somewhat,” said van den Hove in his keynote. “I believe the time to decide lithography options for 14 nm is basically now, and its clear EUV is not ready for the challenge,” he added, in response to a question.

“There is a tremendous effort to solve the [EUV] problems,” said van den Hove. “We believe the problems are not fundamental, they are engineering but it will require time."

Test driving EUV

Earlier this year, an Intel executive said the company believes it could make chips economically even down to 10-nm design rules without EUV, using quad patterning. Intel is believed to generally have higher costs of manufacturing than the rest of the industry, due to the relatively high price for its processors.

Intel, Samsung and TSMC have separately invested billions of dollars this year in ASML which is making the EUV systems. EUV requires a more powerful light source now in development at Cymer, which ASML acquired this year.

With the existing weak light source, today’s EUV systems pattern less than 20 wafers an hour. Chip makers need systems that can pattern more than 100 wafers/hour, said Ronse.

EUVwafers.jpg

ChipRoad.jpg


Chip makers will need to employ new materials or device types at each major node to continue Moore's Law scaling, according to researchers.

A lot of great points made in the article.

The part about multi patterning reducing xtor performance (due to relaxed design rules) really jumped out at me. Apparently "relaxed design rules" involves bigger xtors/features, among other things, at any give node.

So where does Intel go from here?

If lithography becomes more expensive (and even begins to affect performance negatively), I would assume the company's increased emphasis on xtor design and material science becomes that much more important than it was in the past.

But then I begin to wonder how much gain could Intel get from EUV (when finally in production) on top of the strong gains the company is making with xtor design and material science?

Do we get to the point where a device patterned with EUV actually results in a respectable performance increase compared to an identical device quad patterned on 193nm immersion?
 
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HypX

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Oct 25, 2002
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EUV seems hopeless though. Haven't they been promising EUV for over decade? And they still have nothing to show for it.
 

tweakboy

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Good stuff, thanks for the info.

Looks like their gonna hit that speed bum @ 14nm and a 14nm CPU is going to be expensive and not attractive at least to me.
 

Xpage

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IMHO EV will never occur due to secondary electrons being generated. I think the wall for litho will be 10nm, until something groundbreaking happens. Maybe other companies will stop at 14nm if the cost to go to 10nm is as much for 14nm, ie, 200% thus even though you get more wafers it costs as much to make them, only benefit may be lower power and speed increase but those are scaling down each node.

Plus leakage is increasing with each shrink and i think that will be a major issue at 14nm and beyond. That's why if it is not being used, the silicon goes dark, as the leakage is killer
 

bononos

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Aug 21, 2011
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I wouldn't go so far as to call it epic fail. Moore's law is associated with the doubling of performance every 18 months.
 

ShintaiDK

Lifer
Apr 22, 2012
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I wouldn't go so far as to call it epic fail. Moore's law is associated with the doubling of performance every 18 months.

But Moores law got absolutely nothing to do with performance. Its only about transistor count.
 

Idontcare

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Oct 10, 1999
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Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase—and still carry a hefty cost premium--due to the lack of next-generation lithography needed to make them efficiently, according to experts speaking at the International Electron Devices Meeting (IEDM) here on Monday (Dec. 10).

ClockspeedversusPowerConsumptionfor2600kan3770k.png


We've already seen this happen at 22nm, the performance bump was basically half (14%) of the expected performance increase at the same power consumption level, as well as the reduction in power consumption being roughly half (28%) of the expected reduction (50%) for a given performance level.

The part about multi patterning reducing xtor performance (due to relaxed design rules) really jumped out at me. Apparently "relaxed design rules" involves bigger xtors/features, among other things, at any give node.

At the xtor level, where the feature size is a function of trimming the patterned resist prior to the etch process, the patterning issues discussed here would not necessary entail "bigger xtors".

What would become bigger (or shrink less as it were) is the gate and contact pitch. So the xtors may scale to ever smaller dimensions but they won't get packed as close together as one might otherwise expect them to be...this would result in the xtor density not increasing as much as expected per a traditional node shrink as well as performance not improving as much as expected because the wire-delay (xtor-to-xtor signal) would not decrease as much as needed.

Fast xtors wired together by slow wires has been a problem since the dawn of the IC, but the saving grace of having slow wires is that the run length of the slow wires themselves also decreases with a shrink because the gate and contact pitch decreases. (not enough to make up for the increasingly slow wires, but enough to not be critically gating)

The article is suggesting that the slow-wire issue will come to dominate performance scaling at 14nm and beyond. This is certainly true of the foundry processes that are being pursued by TSMC and GloFo where they are taking 20nm BEOL design rules (the slow-wires) and only shrinking the xtors (Finfets) in the shrink to 16nm and 14nm-XM respectively.

Plus leakage is increasing with each shrink and i think that will be a major issue at 14nm and beyond. That's why if it is not being used, the silicon goes dark, as the leakage is killer

Intel managed to keep leakage at 22nm to be comparable to leakage at 32nm. An impressive feat, and it may only be a one-time benefit of going from planar to finfet.

StaticPowerConsumptionVccversusPower.png
 

Idontcare

Elite Member
Oct 10, 1999
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From the OP's linked article, this collage of advanced xtor prototype pics is just pure sex :wub:

ChipRoad.jpg


But Moores law got absolutely nothing to do with performance. Its only about transistor count.

And even then it isn't really about xtor count, it is about the rate of decreasing production-cost per xtor.

(I know you know this, am merely taking the opportunity to expand on it for the benefit of other thread readers who might not be operating with the benefit of having closely studied the original Moore publication)

Graph1.png


Graph3.png
 

Ferzerp

Diamond Member
Oct 12, 1999
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That bar graph of cost per wafer is pretty much in line with expectations, I don't see how that's an impact at all. What it says to me is that the EUV option is potentially larger than Moore's law of a change.
 

ShintaiDK

Lifer
Apr 22, 2012
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ClockspeedversusPowerConsumptionfor2600kan3770k.png


We've already seen this happen at 22nm, the performance bump was basically half (14%) of the expected performance increase at the same power consumption level, as well as the reduction in power consumption being roughly half (28%) of the expected reduction (50%) for a given performance level.

Intel said themselves that IB was just rushed for 22nm in the terms it wasnt optimized at all for it. Would it be better to use Haswell thats designed from the ground up for 22nm and finfets for the compare? Even tho they have much larger uarch differences? Or would it be irrelevant?
 

Stoneburner

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May 29, 2003
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Wasn't moore's law "adjusted" a few years ago, extending the time period from 18 months to 24 months?

I'm not sure why it's called a "law" anyway.
 

Idontcare

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Oct 10, 1999
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Would it be better to use Haswell thats designed from the ground up for 22nm and finfets for the compare? Even tho they have much larger uarch differences? Or would it be irrelevant?

It would be a relevant comparison provided one used the exact same workload (such that the input activity factor was known to not change) and then accounted for the observed IPC variance (such that the output activity factor was normalized).

The "dumb shrink" comparison is already valid though for the same reasons though. I expect performance/watt to improve with Haswell over Ivy Bridge, but I don't expect the clockspeed, voltage, and power-consumption profile to change all that much owing to the dependence on the same underlying device physics. (that would be untrue if Intel were to tweak or alter the underlying process technology that is used for Haswell versus Ivy Bridge of course)
 

Idontcare

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Oct 10, 1999
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Wasn't moore's law "adjusted" a few years ago, extending the time period from 18 months to 24 months?

I'm not sure why it's called a "law" anyway.

It is a rule of thumb that has been adorned the "law" moniker purely as a perfunctory of its popularity.

Law

Finally, the term is sometimes applied to less rigorous ideas that may be interesting observations or relationships, practical or ethical guidelines (also called rules of thumb), and even humorous parodies of such laws.

Examples of scientific laws include Boyle's law of gases, conservation law!s, Ohm's law, and others. Laws of other fields of study include Occam's razor as a principle of philosophy and Say's law in economics. Examples of observed phenomena often described as laws include the Titius-Bode law of planetary positions, Zipf's law of linguistics, Thomas Malthus's Principle of Population or Malthusian Growth Model, Moore's law of technological growth. Other laws are pragmatic and observational, such as the law of unintended consequences.

Some humorous parodies of such laws include adages such as Murphy's law and its many variants, and Godwin's Law of Internet conversations.
 

GreenChile

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Intel seems to laugh at the assertions from this keynote speaker about cost increases. According to Mark Bohr...
Bohr said Intel’s 22-nm FinFET process is cost effective, contradicting report it is 30 to 40 percent more expensive than TSMC’s 28-nm planar process. The addition of FinFET adds only 3 percent to the cost of the process. Its use of 80-nm minimum feature sizes can be made with a single pass of 193-nm lithography tools, making it cost effective.

Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel “is nowhere near that,” he said.

“Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.
http://eetimes.com/electronics-news/4403075/IBM--Intel-face-off-in-22-nm-process-at-IEDM

I find it hard to believe anything about this speaker's predictions. He seems to be just another doom and gloom advocate about the future of silicon technology. These guys have been predicting the end of Moores Law for how long now?
 

Idontcare

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Oct 10, 1999
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Intel seems to laugh at the assertions from this keynote speaker about cost increases. According to Mark Bohr...

http://eetimes.com/electronics-news/4403075/IBM--Intel-face-off-in-22-nm-process-at-IEDM

I find it hard to believe anything about this speaker's predictions. He seems to be just another doom and gloom advocate about the future of silicon technology. These guys have been predicting the end of Moores Law for how long now?

The disconnect is that both van den Hove and Ronse are IMEC employees, not employees of the industry itself per se, and as such they are pretty much clueless in regards to the actual cost structure of an HVM production node at any commercial entity.

This is not a unique occurrence of this problem, in fact the disconnect highlights a very real concern within the industry as it relates to the utility (and support) of maintaining one's membership in these so-called industrial research consortia because the people employed by the consortia tend to have no real "in the trenches" experience or grounding.

Those guys should stick with what they know, and they know the science but they do not know the cost, nor do they really know much about scaling prototype devices into high volume production.

That isn't news to anyone in the industry, but it makes for poor headlines by the trade journalists (who know even less about the economics of the industry than the IMEC folks) and so as a layman you kinda get bombarded with these fancies of imagination instead of the tacit facts on the ground.
 

texasti89

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Jan 15, 2011
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cbn

Lifer
Mar 27, 2009
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At the xtor level, where the feature size is a function of trimming the patterned resist prior to the etch process, the patterning issues discussed here would not necessary entail "bigger xtors".

What would become bigger (or shrink less as it were) is the gate and contact pitch. So the xtors may scale to ever smaller dimensions but they won't get packed as close together as one might otherwise expect them to be...this would result in the xtor density not increasing as much as expected per a traditional node shrink as well as performance not improving as much as expected because the wire-delay (xtor-to-xtor signal) would not decrease as much as needed.

Fast xtors wired together by slow wires has been a problem since the dawn of the IC, but the saving grace of having slow wires is that the run length of the slow wires themselves also decreases with a shrink because the gate and contact pitch decreases. (not enough to make up for the increasingly slow wires, but enough to not be critically gating)

The article is suggesting that the slow-wire issue will come to dominate performance scaling at 14nm and beyond. This is certainly true of the foundry processes that are being pursued by TSMC and GloFo where they are taking 20nm BEOL design rules (the slow-wires) and only shrinking the xtors (Finfets) in the shrink to 16nm and 14nm-XM respectively.

Thanks for the great insight on this matter.
 

SunRe

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Dec 16, 2012
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Intel said themselves that IB was just rushed for 22nm in the terms it wasnt optimized at all for it. Would it be better to use Haswell thats designed from the ground up for 22nm and finfets for the compare? Even tho they have much larger uarch differences? Or would it be irrelevant?

Actually a more revealing comparison would be between some i7-3930K and the soon to be released Ivy Bridge E / or the XEON counterparts. Presumably the architecture would be the same and by now Intel would've cleared all the wrinkles in the 22nm process.