EE Times: Intel's 22-nm tri-gate SoC, how low can you leak?

[cbn]

http://www.eetimes.com/electronics-...ate-SoC---how-low-can-you-leak--?pageNumber=0

Sylvie Barak
12/10/2012 4:30 PM EST

SAN FRANCISCO -- Intel will describe its 22-nm tri-gate (FinFET) SoC technology for mobile applications Monday (Dec. 10) at the International Electron Devices Meeting (IEDM) here.

The chip maker introduced a CPU version of its 22-nm offering in June, but Intel senior fellow Mark Bohr said in an interview that the recipe has been tweaked in order to scale down to a more mobile, ultra-low leakage version.

The change means Intel will now be able to boast product support from high performance servers down to cell phones on a tri-gate 22-nm process, with transistors covering a wide range of performance barriers.

Intel’s new SoC technology also includes high voltage I/O transistors, precision resistors, capacitors and inductors that were not included on the original CPU version of the chip.

The SoC’s will be ready for high volume manufacturing in 2013, Bohr said.

Intel had tended to focus heavily on performance, but is now looking to widen its transistor scope. On the performance side of the scale is the CPU version of Ivy Bridge, which also exhibits higher power leakage. On the lower end of the scale, however, Intel is seeking to offering a range of choices.

“There isn’t just one version of our SoC technology," Bohr said. "We [will] offer a rich menu of options to pick and choose from, both different transistor options and different interconnect options,” said Bohr.

Bohr said it was now abundantly clear that 22-nm tri-gate SoCs outperformed 32-nm planar devices by a margin of 20 to 65 percent, while covering four different orders of magnitude in current leakage.

Intel said its 22-nm tri-gate product also exhibits superior short channel control, with optimum sub-threshold slope and drain-induced barrier lowering (DIBL). The sub-threshold slope allows for low leakage but could also function well at low voltage, making them “much better than the very best planar devices," Bohr added.

Bohr said the low numbers for DIBL seen in testing were a measure of good performance in short channel control, with the new SoC pulling in DIBL numbers of 30 to 35mVs, while comparable products had DIBL’s closer to the 100mV range.

Bohr said that when Intel had first announced it would be using tri-gate devices, other companies had argued that FinFET transistors would not aid analog design. “Well, they’re wrong,” declared Bohr.

For analog designers, he asserted, an important transistor metric is trans-conductance by power out (GM x Rout). Bohr said that while this value had been steadily degrading over the past few generations, it had shot up again in 22-nm trigate SoCs, making it easier for analog circuit designers to use than Intel’s previous three generations of planar technology.

Bohr also touted the technology's advanced passive features, including precision resistors, MIM capacitors and high Q inductors.

Scalable roadmap

Ultimately, said Bohr, the distinction between regular processors and SoCs is blurring, with even CPUs like Ivy Bridge incorporating typical SoC elements like multiple computing cores, graphics, high performance IO circuits and cache. SoC,s however, are still taking those components to the extreme. “It’s a matter of degree,” Bohr said.

Indeed, Intel’s SoC is almost identical to its CPU version in terms of structure, including only some “minor tweaking” to provide either the lower leakage or higher volatage. It could even be described as a “superset” of the CPU version with expanded features.

The SoC and CPU versions share many of the same process features; the same transistor structure and pitch along with similar interconnect and fab process equipment. “These two technologies can be run side by side in the same factory,” said Bohr, noting that all the yield learning for Ivy Bridge had been translatable.

Bohr acknowledged that SoCs had presented Intel with new challenges. “When you talk about leakage, once you get down into the below 30 pico amp range, you have to deal with multiple sources of leakage, whether it’s through the gate oxide or leakage from source to drain or leakage from the drain to the substrate,” he said, adding that it had taken a lot of “tweaking an balancing” to finally get it right.

The turning point had finally been reached, he said, with the firm’s 32-nm Medfield SoC. “You’ll see some pretty impressive SoC products coming next year on the 22nm generation,” he said.

In terms of how Intel’s 22-nm SoC process stacks up against the 28-nm low power or forthcoming 20-nm processes from TSMC, Bohr claimed Intel had “far surpassed” the performance and low leakage capabilities of competitors. “We have a significant lead over our competitors,” he asserted.

Intel is also banking on he new technology process having a long tail. “We know that it’s scalable to 14-nm,” he said, concluding that tri-gate was not only a big power advantage for Intel’s CPUs, but for other low power SoCs.

Great article. In a nutshell, Intel has developed four 22nm processes (HP, SP, LP, ULP), but notice the Intel Logic Technology Roadmap only has two listed:

1. P1270 for the CPU 22nm process
2. P1271 for the SOC 22nm process

I am assuming P1270 will use 22nm HP, but what 22nm process will P1271 use? SP, LP or ULP?

Looking at the first graph (below) we see Server listed as having a leakage of "1" and pocket device is listed as having a leakage of .001x. (This is a difference of 1000 for leakage)

With the HP process listed as 100 nano amps leakage (see chart below) that would imply a leakage of 100 pico amps is needed for "pocket device".

Going by the above chart, I'm thinking Intel's 22nm LP (at only 30 pico amps leakage) should easily be able to fill this need. Although with that said, it does appear the 22nm ULP process (with only 15 pico amps leakage) would be even better.

Other interesting topics in the article are the effect of FinFET on analog design as well as FinFET being scalable to 14nm.

 

[Idontcare]

I am assuming P1270 will use 22nm HP, but what 22nm process will P1271 use? SP, LP or ULP?

It will use all three, meaning it is up to the design target of the SoC and the design engineers selection of components when they design the SoC.

 

[epidemis]

Interesting, I wonder what kind of radio-performance they have. Those are always a source of power drain

 

[cbn]

It will use all three, meaning it is up to the design target of the SoC and the design engineers selection of components when they design the SoC.

Thank you. I wasn't clear on how restrictive the rules were for mixing high leakage and low leakage xtors.

So, for example, a ULV Haswell SOC probably uses SP, but the designers theoretically could use LP and ULP for certain components on the SOC if that process was available in the fab at that time the chip was built.

More info:

http://www.pcmag.com/article2/0,2817,2413059,00.asp

Designers of Intel's next-gen SoCs will have a great deal of flexibility in mixing and matching different types of transistors, high-density interconnects, and RF/mixed-signal features, Mulloy said.

The authors of the IEDM paper elaborated further, saying that Intel is the first company to develop "a leading edge 22nm SoC process technology featuring 3D tri-gate transistors which employs high speed logic transistors, low standby power transistors, and high-voltage tolerant transistors simultaneously in a single SoC chip to support a wide range of products, including premium smartphones, tablets, netbooks, embedded systems, wireless communications, and ASIC products."

The upshot for Intel is if they get Atom SOC (or more accurately the LP/ULP process) on the bleeding edge node (rather than lagging), there may be some side benefits for the laptop SOCs.....if those laptop SOCs can, in fact, benefit from a xtor with lower leakage than SP for certain features.

But what parts of a ULV Laptop SOC could benefit from LP and ULP process? (Going by the assumption the basic core itself using SP)

 

[cbn]

For those interested, here is some great animation I found on planar vs. 3D xtor:

http://www.youtube.com/watch?feature=player_detailpage&v=YIkMaQJSyP8#t=134s (animation of planar xtor)

http://www.youtube.com/watch?feature=player_detailpage&v=YIkMaQJSyP8#t=180s (Animation of 3D xtor. Mark Bohr specifically mentions the benefit of the gate wrapping around the stream of electron flow. This helps control as the geometries get smaller.)

 

[Idontcare]

Thank you. I wasn't clear on how restrictive the rules were for mixing high leakage and low leakage xtors.

So, for example, a ULV Haswell SOC probably uses SP, but the designers theoretically could use LP and ULP for certain components on the SOC if that process was available in the fab at that time the chip was built.

Yep. The restrictions are just in the cost aspects of the additional masks required for the mixing and matching, plus it is a cycle-time adder to go through the extra process steps as needed to fabricate the various flavors of xtors.

You can get quite fancy and create some real whiz-bang fancy SoCs, but that fancy drives up production costs once designed, as well as driving up the design costs themselves (it takes more time to optimize the more complex design), and drives up the validation expenses and risk of needing all the more respins...all of which can push out the timeline for getting the SoC to market by months if not years.