ee folks: simple current mirror question - how can current be running on 2nd xtor?

[LordSnailz]

If I look at the setup for MOSFET current mirror on http://en.wikipedia.org/wiki/Current_mirror

I get the idea the Iout = Iref since both transistors have the same Vgs but how can current flow in T2 if Vds = 0?

I'm trying to simulate this in SPICE and I'm getting 0 current at the output, which is what I expect but for some reason wiki says differently.

For Iref, I added a current source to the drain of T1.

Any suggestions?

 

[PottedMeat]

Did you hook up the T2 side of the circuit?

I did a quick sim with SwitcherCAD and copied the Wiki circuit. I added a 100mA current source to the T1 side and attached a 5V voltage source to the drain of the T2 side. The MOSFETs were a pair of FDS6680A or whatever models you have handy.

Simulating, Iref = Iout.

 

[LordSnailz]

cool, I'm using switcherCAD as well and what you said made more sense, I needed a Vd on the T2 side. Weird though, I'm still getting mismatch currents. With 100mA, your Vgs is about 100V right? If that's the case, you would need at least 100V on the T2 drain side to get the same current no?

I'm just confused, if this is a current mirror then why do we need a voltage source on the drain of T2, it's almost like tying the drain and gate of T2 to the gate and drain of T1.

 

[PottedMeat]

Note - I've never taken classes on Integrated Circuit Design ( assuming this is what you're talking about )

I think the idea is just that you have a specified current you want to push through a load, so you hook up the current mirror configuration with Iref in T1. The load with its appropriate voltage source is connected in series into the drain of T2. I think the connected gates and common Vgs will change the Rds of T2 when combined in series with the load have Iref flowing though them.

My Vgs is 2.256V - Did you hook up the current source directly to T1 and the other end directly to ground?

 

[LordSnailz]

I've uploaded the schematic here - http://pics.bbzzdd.com/users/lordsnailz/curr_mirror.JPG
btw, do you know how I can change the Vt of the NMOS?

 

[Born2bwire]

Originally posted by: LordSnailz
cool, I'm using switcherCAD as well and what you said made more sense, I needed a Vd on the T2 side. Weird though, I'm still getting mismatch currents. With 100mA, your Vgs is about 100V right? If that's the case, you would need at least 100V on the T2 drain side to get the same current no?

I'm just confused, if this is a current mirror then why do we need a voltage source on the drain of T2, it's almost like tying the drain and gate of T2 to the gate and drain of T1.

You need a V_{DS} >= V_{GS} for a current mirror to work because you need to bias the current source transistor into saturation. If you were to do a voltage sweep of V_{DS} across the current source, you would see the current slowly ramp up between 0<=V_{DS}<V_{GS} since the transistor is in triode. At V_{GS}, you get your ideal current output. Above V_{GS}, the current will slowly ramp up due to channel length modulation.

 

[LordSnailz]

I agree that the T1, the transistor with the current source should be in saturation; that's why it's diode connected, gate tied to drain. But what I'm confused about is the T2 side, I thought just by setting the Vgs the same as T1 I would get the same current but then again this doesn't make sense since Vds is 0.

If I have to bias Vds of T2 doesn't it defeat the purpose of the current mirror?

 

[Born2bwire]

Originally posted by: LordSnailz
I agree that the T1, the transistor with the current source should be in saturation; that's why it's diode connected, gate tied to drain. But what I'm confused about is the T2 side, I thought just by setting the Vgs the same as T1 I would get the same current but then again this doesn't make sense since Vds is 0.

If I have to bias Vds of T2 doesn't it defeat the purpose of the current mirror?

I am talking about T2, your current source. For T2 to be in saturation, V_{GS}>V_T and V_{DS}>=V_{GS}. So for the current mirror to work, you need to bias T2 into saturation.

Go through and actually derive the current output of the source. You should see instantly that the large signal analysis is only valid if both the reference transistor and the current source transistors are in saturation.