This is because of the way PCI is defined - ALL the PCI (and AGP) hardware have only four PCI (!) interrupt lines to share. This means add as many PCI bridges as you want, you'll never have more than INTA, INTB, INTC, INTD. Meaning that with more than four PCI devices in the system, you'll always have shared interrupts. Newer chipsets relieve the problem a little bit by separating their integrated USB and sound stuff from these four lines, but for everything in PCI slots, it has to be done in said way - everything else would violate the PCI specification.
On an x86 PC, these four are then routed by the PCI-to-ISA bridge onto a maximum of four ISA IRQs. There, more than one INTx can be routed together onto a single IRQ. THIS, and only THIS routing can be influenced by system BIOS.
Meaning that there are two kinds of interrupt sharing for PCI devices - (1) two slots using the same INTx line on the PCI side, (2) INTx lines routed onto the same IRQ for lack of available IRQs.
The latter can be avoided by keeping four ISA IRQs available using system BIOS, but that's all you'll get. The PCI system can never use more than four.
Remember, interrupt sharing capability is a REQUIREMENT in the PCI bus specification for any PCI device! This is not a conflict! (Which doesn't mean that after all those years of PCI, there are still enough drivers around that don't care ...)
Regards, Peter
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