Dual or more DDR channels

[hoe4damoney]

Is nForce the only consumer level chipset to be released in the near future with dual ddr channels?

I think i read somewhere the reason that chipset makers havent implemented this quicker is that it requires a 6 layer motherboard design.

I'm also confused about the seeming similarity between multiple FSB channels eg. the (ep6?) bus from AMD and multiple DDR (or even rambus) channels.

Anyone care to educate this simple soul?

 

[Remedy]

VIA has a Dual and quad channel controller coming with their new fleet of chipsets.

 

[AndyHui]

The Alpha EV6 bus used by AMD for its Athlon and Duron processors is simply a bus that sends data on the rising and falling edge of the clock signal. Meaning that for every clock cycle, it sends data twice. This has nothing to do with multiple FSB channels.

DDR RAM also uses the same principle of sending data twice on every clock cycle, effectively doubling the bandwidth. Dual Channel DDR is different, in that there are two separate buses to RAM which are multplexed to give twice the bandwidth of a single channel.

The problem with dual RAM channels is that more PCB layers are needed to achieve a stable design. A 6 layer PCB motherboard is more expensive to produce than a standard 4 layer PCB design.

For more information about DDR SDRAM, please read this FAQ article.