Dual Core Yonah to come equipped with HT and smart cache.

[Keysplayr]

THG Article

But does not yet support 64-bit.

 

[stevty2889]

"The 65 nm production process, internally named P1262, is implemented in the manufacturer's D1D fab located in Hillsboro, Oregon."

Err it's the 1264 proccess, 1262 is the 90nm proccess that prescott runs on..but other than that, everything looks pretty accurate.

 

[RichUK]

is thing going to be for laptops only then, or is it going to be for the desktop aswell

 

[Duvie]

Probably someone will build and adpater...Doesn't matter too much as we know what the cost of INtel laptop chips are in reference to other chips....


I also wonder what are oging to the changes to the Yonah core to correct some of the weaknesses of the P-M's??? I mean shared cache is something they should have done with the smithfields if they were not so rushed getting the chip out and just would have done it right.

 

[Keysplayr]

Originally posted by: Duvie
Probably someone will build and adpater...Doesn't matter too much as we know what the cost of INtel laptop chips are in reference to other chips....


I also wonder what are oging to the changes to the Yonah core to correct some of the weaknesses of the P-M's??? I mean shared cache is something they should have done with the smithfields if they were not so rushed getting the chip out and just would have done it right.

Wider is better. 🙂 They are making it wider. More registers. They are improving the IPC of the chips so I guess the ALU's will be beefed up. Dunno. SSE3. 667FSB. ummm. 65nm.
So this thing is going to be a cross between a P4 and a Pentium M? Gonna be a strange chip if it has HT with nowhere near the pipeline length..

 

[bjc112]

Originally posted by: keysplayr2003

Originally posted by: Duvie
Probably someone will build and adpater...Doesn't matter too much as we know what the cost of INtel laptop chips are in reference to other chips....


I also wonder what are oging to the changes to the Yonah core to correct some of the weaknesses of the P-M's??? I mean shared cache is something they should have done with the smithfields if they were not so rushed getting the chip out and just would have done it right.

Wider is better. 🙂 They are making it wider. More registers. They are improving the IPC of the chips so I guess the ALU's will be beefed up. Dunno. SSE3. 667FSB. ummm. 65nm.
So this thing is going to be a cross between a P4 and a Pentium M? Gonna be a strange chip if it has HT with nowhere near the pipeline length..

Is there a disadvantage to having HT with a shorter pipeline?

 

[stevty2889]

They would have to implement hyperthreading in a differant way than they did with the P4 for it to be effective, otherwise it won't be much of a benifit.

 

[dmens]

yonah does not have SMT and its not 64-bit enabled because it was designed a fair while back....

also, the core concepts behind smt remain consistent between p4 and p6 designs.

 

[rgreen83]

However, we also heard in the past that the integration of 64-bit capability would have increased the size and power consumption of the chip.

One question, how much could adding 64 bit support really add to power draw? If its running in a 32bit env. anyways, wouldnt those parts of the chips just lie dorment? And I dont think its really going to add all that much to the transistor count, not enough to make a big difference against the other 150million. It seems intel is blowing smoke up our asses on that one.

 

[Keysplayr]

Originally posted by: rgreen83

However, we also heard in the past that the integration of 64-bit capability would have increased the size and power consumption of the chip.

One question, how much could adding 64 bit support really add to power draw? If its running in a 32bit env. anyways, wouldnt those parts of the chips just lie dorment? And I dont think its really going to add all that much to the transistor count, not enough to make a big difference against the other 150million. It seems intel is blowing smoke up our asses on that one.

There would be a large increase in transistors and the fact of having twice the registers accepting calculation requests at the same time would consume a bit more power. I don't think it would kill the Yonah with an increase of power consumption if it is only going to consume 25W as it is. How much more could it increase? Lets go for broke and call it double at 50W. Still very low.

 

[Lonyo]

Originally posted by: keysplayr2003

Originally posted by: rgreen83

However, we also heard in the past that the integration of 64-bit capability would have increased the size and power consumption of the chip.

One question, how much could adding 64 bit support really add to power draw? If its running in a 32bit env. anyways, wouldnt those parts of the chips just lie dorment? And I dont think its really going to add all that much to the transistor count, not enough to make a big difference against the other 150million. It seems intel is blowing smoke up our asses on that one.

There would be a large increase in transistors and the fact of having twice the registers accepting calculation requests at the same time would consume a bit more power. I don't think it would kill the Yonah with an increase of power consumption if it is only going to consume 25W as it is. How much more could it increase? Lets go for broke and call it double at 50W. Still very low.

They are saying that it will consume less than Dothan, so with 64bit ext it'd probably be about the same I would guess.

 

[Keysplayr]

Originally posted by: Lonyo

Originally posted by: keysplayr2003

Originally posted by: rgreen83

However, we also heard in the past that the integration of 64-bit capability would have increased the size and power consumption of the chip.

One question, how much could adding 64 bit support really add to power draw? If its running in a 32bit env. anyways, wouldnt those parts of the chips just lie dorment? And I dont think its really going to add all that much to the transistor count, not enough to make a big difference against the other 150million. It seems intel is blowing smoke up our asses on that one.

There would be a large increase in transistors and the fact of having twice the registers accepting calculation requests at the same time would consume a bit more power. I don't think it would kill the Yonah with an increase of power consumption if it is only going to consume 25W as it is. How much more could it increase? Lets go for broke and call it double at 50W. Still very low.

They are saying that it will consume less than Dothan, so with 64bit ext it'd probably be about the same I would guess.

I could also be that they didn't have enough time? to implement 64 bit on Yonah. Or maybe, not enough die space even a 65nm. Could be many different reasons.

 

[MDme]

No 64bit. i'm not sure that's a good idea since mosts Longhorn will be 64 bit only. who in his right mind would buy a CPU that doesn't run on new OS'es

 

[carlosd]

Originally posted by: stevty2889
They would have to implement hyperthreading in a differant way than they did with the P4 for it to be effective, otherwise it won't be much of a benifit.