Drawbacks from Hyper-Threading

Aug 26, 2013
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#1
Are there any major consumer relevant drawbacks / cons in the implementation of hyper-threading? Essentially, what has to be sacrificed in the doubling of a chips total threads? Similarly, hyper-threading and competing virtual core solutions seems to be a no brainer to amplify a chips performance in certain scenarios without increasing the die size, so why is this not yet a commodity in the chip market?

I know there are probably major flaws in the logic behind my assumptions, but I have failed to find a suitable answer to this question that has been knawing at my brain regarding the entire industry!
 
Apr 22, 2012
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#2
There isn't any downsides for end users. You may see a tiny downside if you run something like Linpack. But that's pretty much the only thing I can think on.
 

Zodiark1593

Platinum Member
Oct 21, 2012
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#3
Power consumption is the most probable, perhaps due to the additional hardware to enable it. It used to be that Hyperthreading incurred a minor single-thread performance hit, but between wider cores and modern OSs built to handle the threads, this is no longer an issue.
 
Aug 26, 2013
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#4
Power consumption is the most probable, perhaps due to the additional hardware to enable it. It used to be that Hyperthreading incurred a minor single-thread performance hit, but between wider cores and modern OSs built to handle the threads, this is no longer an issue.
Then is it possible that we will see the widespread use of virtual cores in mobile, such as multiple virtual cores being used with fewer physical cores in a big.LITTLE setup? Or are the differences between mobile and desktop workloads too great for such an analogy to be plausible / worthwhile? Also, is there a future scenario in which Intel drops half the cores in their lower end processors to free up die, but adds HT, and then proceeds to increase the size of their integrated graphics?

Also, thanks for the replies. I've been really caught up on this subject lately and you have been of great help.
 
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Shmee

Memory and Storage, Graphics Cards
Super Moderator
Sep 13, 2008
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#5
Perhaps lower OC with HT on?
 
Aug 25, 2001
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#6
Power consumption is the most probable, perhaps due to the additional hardware to enable it. It used to be that Hyperthreading incurred a minor single-thread performance hit, but between wider cores and modern OSs built to handle the threads, this is no longer an issue.
It used to be that one could see resource-starvation inside the cores for certain threads, if their "pair" thread was a heavy resource user.

This changed, I believe in IVB, where HT could more fairly allocate the internal chip resources, and in HSW, they added the feature that if one thread was running without a "pair" thread, then it could allocate more of those core resources, but then they would be freed up if another thread got scheduled with that thread.

And overall resource counts internal to the core got increased in SKL, so it's even less of a problem.
 
Aug 25, 2001
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#7
such as multiple virtual cores being used with fewer physical cores in a big.LITTLE setup?
As far as I am aware, HT (SMT) is orthagonal to the issues surrounding BIG.little. One can have one with or without the other.
 

Zodiark1593

Platinum Member
Oct 21, 2012
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#8
As far as I am aware, HT (SMT) is orthagonal to the issues surrounding BIG.little. One can have one with or without the other.
Exclusive big core designs like Apple's A9 would be the primary benefactors from SMT. Kyro would also probably have been a pretty good candidate as they focus on power gating on a per-core basis and per-core performance tends to be pretty high (if due to high clocks).

Not sure how SMT would benefit mobile though. Multitasking is rarely demanding on these platforms that they'd choke a pair of competent cores, let alone a quad.
 
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Erithan13

Senior member
Oct 25, 2015
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#9
On this subject, am I right in saying that all Skylake/Haswell etc cores have the HT hardware built into them, only it's disabled on the i5s/Celerons/Pentiums? So it's not like the core was designed and then HT added on the i3s and i7s, rather the core was very much designed with HT in mind but in such a way the circuits could be disabled where needed for certain models. So there'd be nothing theoretically stopping Intel from making all subsequent Skylake CPUs have HT enabled (although that would seriously mess up the segmentation of the i3>i5>i7 I know....I'm basically wondering if there's a technical reason for i5s not having HT rather than a marketing/business one).
 
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Zodiark1593

Platinum Member
Oct 21, 2012
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#10
On this subject, am I right in saying that all Skylake/Haswell etc cores have the HT hardware built into them, only it's disabled on the i5s/Celerons/Pentiums? So it's not like the core was designed and then HT added on the i3s and i7s, rather the core was very much designed with HT in mind but in such a way the circuits could be disabled where needed for certain models. So there'd be nothing theoretically stopping Intel from making all subsequent Skylake CPUs have HT enabled (although that would seriously mess up the segmentation of the i3>i5>i7 I know....I'm basically wondering if there's a technical reason for i5s not having HT rather than a marketing/business one).
All Skylake cores (well, any big core since the first i7) has HT circuitry in hardware regardless of sku. The decision to disable it or not is solely a business decision.
 
Apr 22, 2012
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#11
On this subject, am I right in saying that all Skylake/Haswell etc cores have the HT hardware built into them, only it's disabled on the i5s/Celerons/Pentiums? So it's not like the core was designed and then HT added on the i3s and i7s, rather the core was very much designed with HT in mind but in such a way the circuits could be disabled where needed for certain models. So there'd be nothing theoretically stopping Intel from making all subsequent Skylake CPUs have HT enabled (although that would seriously mess up the segmentation of the i3>i5>i7 I know....I'm basically wondering if there's a technical reason for i5s not having HT rather than a marketing/business one).
HT have been segmented since the P4. Core 2 actually had HT but disabled for all parts. All Skylake parts also got an EDRAM controller.
 
Aug 26, 2013
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#12
Is there a limitation on how many virtual cores one can have for every physical one? For example, for shits and giggles could Brian Krzanich decide he wants to upgrade his sick gaming build with a single core, 8 thread processor (the i9 1337K with quad HT) knowing full well he will not have equal performance to a true octo-core processor?
 
Apr 22, 2012
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#13
Is there a limitation on how many virtual cores one can have for every physical one? For example, for shits and giggles could Brian Krzanich decide he wants to upgrade his sick gaming build with a single core, 8 thread processor (the i9 1337K with quad HT) knowing full well he will not have equal performance to a true octo-core processor?
You can more or less have as many as you like. Xeon Phi got 4 per core. Sparc and Power have done 8 per core.

You just need a wide enough core with a lot of regularly wasted execution units for it to work. (This is also why Linpack doesn't scale with HT).
 
Aug 25, 2001
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#14
Core 2 actually had HT but disabled for all parts.
Source please? I've been on these forums for a long time, and I have never heard that. Did Pentium-M have HT? I didn't think so on that core either.
 
Jul 25, 2014
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#15
Hyperthreading produces a bit more heat when the extra threads are being used and it may take a bit more voltage for a CPU with HT to be stable at a given frequency. That's from the increased work the cores are doing and the extra stress that increase causes, respectively.
 

waffleironhead

Diamond Member
Aug 10, 2005
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#16
Hyperthreading is great as long as you don't saturate the shared resources.
 
Apr 22, 2012
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#17
Source please? I've been on these forums for a long time, and I have never heard that. Did Pentium-M have HT? I didn't think so on that core either.
Pentium-M didn't have it.

Not going to dig up a source on a 10 year old part.
 

jpiniero

Diamond Member
Oct 1, 2010
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#18
So there'd be nothing theoretically stopping Intel from making all subsequent Skylake CPUs have HT enabled (although that would seriously mess up the segmentation of the i3>i5>i7 I know....I'm basically wondering if there's a technical reason for i5s not having HT rather than a marketing/business one).
It's possible that models without HT are binned with models that the HT portion is busted but that would be pretty low number I think. It's more likely fused off for marketing purposes.
 
Apr 22, 2012
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#19
It's possible that models without HT are binned with models that the HT portion is busted but that would be pretty low number I think. It's more likely fused off for marketing purposes.
If HT is busted so is the core. HT is only disabled due to segmentation.

Example from P4.
 

SPBHM

Diamond Member
Sep 12, 2012
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#20
Source please? I've been on these forums for a long time, and I have never heard that. Did Pentium-M have HT? I didn't think so on that core either.
I also never heard of this before, it also wouldn't make sense for them to never enable even for some Xeon models, unless HT was not there or broken.

I mean Willamette P4 had HT but was never used, but some Xeon parts based on the same core had it enabled.

as others have mentioned HT will probably increase power usage, and while rare these days it still can reduce performance in some conditions
 

2is

Diamond Member
Apr 8, 2012
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#22
This is the first I've heard of a disabled HT feature on Core 2 as well.
 

Tuna-Fish

Senior member
Mar 4, 2011
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#24
If HT is busted so is the core. HT is only disabled due to segmentation.
In Skylake Intel duplicated some of the back-end resources and gave each of the two threads a dedicated one. It would now be theoretically possible for there to be a defect that killed the second thread while not hurting the first.

I don't know if Intel uses this to bin any chips, though.
 

NTMBK

Diamond Member
Nov 14, 2011
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#25
Core 2 never had SMT. It was only reimplemented on Nehalem.
 

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