DRAM Vs. SRAM

[Woodchuck2000]

I've been trying to figure this one out and can't quite get my head round the reason. As I understand it, DRAM is effectively a transistor and a capacitor hooked together which stores a state for a few milliseconds. SRAM is a bistable arrangement of about 4-6 transistors that holds its charge until power is turned off. Why does this make DRAM slower and what exactly is meant by "Refreshing" DRAM?

Explanations very welcome as my brain hurts!

 

[Peter]

DRAM needs to be refreshed because the capacitor's charge gradually fades away through leakage. So you need to rewrite the bit cell periodically to retain the data.

 

[Woodchuck2000]

But why does that make it necessarily slower than SRAM? Is it simply because a proportion of clock cycles are wasted on refreshes? Even if it's refreshed every nanosecond, for RAM running at 100MHz surely that's only a 1% reduction in efficiency...

 

[Peter]

Where did I say that's what makes it slower?

 

[TuxDave]

In order to make a read on a DRAM, you essentially have to rely on charge sharing from the bitlineand the memory cell. The DRAM bitlines are precharged to VDD and on a read, the memory cell is opened and if the memory actually contained a zero, some of the charge is moved from the bitline into the memory cell. So you'll see a smaaaaall dip in the voltage of the bitline. This small dip has to be detected by a very precise sense amp and that is where the slowness comes in.

On the other hand, when reading from an SRAM, you have an active device pulling down on the bitline and so the bitline should dip even more than that of the DRAM. This voltage difference will be faster to detect since the switching speed in a sense amp is proportional to the voltage difference.



* Caution: I get bitline and wordline confused a lot so excuse any mistakes in that regard.

Editted for English Speakers 😛

 

[Fox5]

Originally posted by: Woodchuck2000
But why does that make it necessarily slower than SRAM? Is it simply because a proportion of clock cycles are wasted on refreshes? Even if it's refreshed every nanosecond, for RAM running at 100MHz surely that's only a 1% reduction in efficiency...

I think SRAM is faster latency, not higher bandwidth.(though if dram goes high enough, shouldn't it be lower latency?)

Didn't old computers use to use SRAM and it was very slow and expensive?

 

[Woodchuck2000]

TuxDave - That's the first plausible answer I've found! That would definitely make a degree of sense...

Fox5 - SRAM can run at much higher frequencies hence being used as full-speed cache on CPUs. I believe this has something to do with DRAM's need to be refreshed but I'm not entirely sure what the technical answer is.

Anyone else have any insight?