Does FSB really matter that much?

SWScorch

Diamond Member
May 13, 2001
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I was talking to my boss about S@H and how I want a mobo with a faster bus speed so I could crunch WUs faster. We then got into a rather lenghty discussion about the merits of a higher FSB and how it relates to memory bandwidth and the like. He said that he didnt think FSB would matter all that much, as long as the memory was running fast. A valid point, to be sure, but afterwards I realized that theres one thing I'm a bit fizzy on. With memory running at 133 and a FSB of 100, its really not doing much good because the CPU is only recieving 3/4 of the data from the memory every cycle. EG- the memory returns bits to the northbridge at 133MHz, but the CPU retrieves the bits at 100MHz; its waiting for extra bits. Right? Or is the "PC" specification of the memory referring to the speed the memory communicates with the CPU, and the FSB really doesnt matter? EG- even with a FSB of 100, PC133 ram will still talk to the CPU at 133MHz.

So I decide to overclock my 1Ghz Athlon a wee bit more; from 1300 to 1365, on a 105MHz FSB. This in turn bumped the memory up to 140MHz. My WU times have dropped significantly, and my machine is pumping out a substantial amount more than it did before. Now, is this primarily dependant on the FSB being bumped or the memory?
 

Baldy18

Diamond Member
Oct 30, 2000
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In my nonprofessional oppinion I would say it is due to the increase in FSB.
 

TuffGuy

Diamond Member
Jul 6, 2000
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seti is HIGHLY fsb dependent. at 1440mhz and 160mhz fsb, my benchmark was 3h32min. at 1470mhz and 173mhz fsb, it dropped to 3h22min.

benchmarks
 

networkman

Lifer
Apr 23, 2000
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FSB is important, although L2 cache is even more important! ;)

Example: I have one system that is a Dual p3-733@787 via a 143 fsb - fair enough. However, I also have a Dual p2-400@400 XEON system with each chip having 2 MEG of L2 cache - the Xeon system, even being a 100 fsb and 387 MHz slower per CPU is STILL crunching units slightly faster than the Dual p3 system! :Q

No kidding. ;)

 

SWScorch

Diamond Member
May 13, 2001
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Okay so let me see if this correct... (I cant believe I went this long without really thinking about this)

The northbridge connects the CPU and memory. The memory speaks to the northbridge at a speed determined by the PC setting of the SDRAM. The northbridge then shares this data with the CPU at a frequency determined by the Front-Side Bus. Or is the path between the memory and the CPU a direct one? (i assume not; otherwise FSB and memory sped would always be synchronous)
 

Orange Kid

Elite Member
Oct 9, 1999
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<< Example: I have one system that is a Dual p3-733@787 via a 143 fsb - fair enough. However, I also have a Dual p2-400@400 XEON system with each chip having 2 MEG of L2 cache - the Xeon system, even being a 100 fsb and 387 MHz slower per CPU is STILL crunching units slightly faster than the Dual p3 system! >>



The Xeons are faster because the whole process will fit into the cache on the "chip"---------there is no need to access the memory at all on that system.......so in essence you could say that the FSB is what ever the speed the cache is..........also there is no sharing of this memory and both chips have full bandwidth to work with..............the P3's have to share the FSB to the memory there by decreasing it further
 

Assimilator1

Elite Member
Nov 4, 1999
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SWScorch
That seems right to me:)
Btw I would say that both mem bus & FSB are important for SETI ,so a 100/133 rig will be slower than a 133/133 rig ,this is partly due to better bandwidth but significantly it is also due to lower latencies of the synchronised bus of tha latter system.
When Athlon Tbirds went from 100/133 to 133/133 they saw a significant boost in peformance for anything memory intensive ,I can't wait for the 166/166 CPU's ;)
 

ElFenix

Elite Member
Super Moderator
Mar 20, 2000
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memory bus and FSB should be fast and synchronous for best performance. fast because, well, fast is better. a lot better. the processor is waiting most of the time in seti, as evidenced by the large cache xeon phenomenom. (/me wonders how fast a p4 xeon would eat a seti unit!)


synchronous because a) you're being held back by which ever is slower (see p3 with rdram, though rdram had about 55% more bandwidth the i820 p3s weren't any faster) and b) some chipsets implement wait states to make the async connection increasing latency.


now... the athlon has a DDR FSB so its theoretically going 200 MHz so its your ram thats slower.