Does anyone know the answer to this question?

[imported_Helios]

Consider a 32 bit microprocessor that has an on-chip 16 KByte four-way-set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?

I have a vague idea, but need serious help.

 

[Bassyhead]

Not truly highly technical, and you won't learn anything if the forum does your homework for you. What do you have so far to work from? I'm pretty sure that with a set associative cache you can put the cache block anywhere in the "line". The "line" you will put the block in is the address modulo the number of "lines" you have. I might be wrong, you should check your textbook or something.

 

[shuan24]

the block diagram is easy. Just imagine an array of 4K lines by 4 slots. That is your cache. Then you read Bassyheads post to figure out the rest.

 

[MisterChief]

Way above my understanding...

 

[CTho9305]

Originally posted by: MisterChief
Way above my understanding...

It's actually really simple If I ever got around to finishing this (particularly this page I could just point you there). Unfortunately, I have way too much work this semester to make much progress.

 

[DiscoBiscuit]

this sounds like one of my CPU-Architecture lessons was fun but unfortunetly over in the UK there isnt much CPU engineering jobs happening..

if you really need help i can always look up my old notes - sounds like one of my mock exam questions i had for comp sci

 

[Calin]

A cache will store "words" from main memory into it. A "word" would be (in your example) 16 bytes. The "words" (lines in cache" are made as big as possible, to decrease the size of the translation buffers that shows what bytes from main memory are imaged in cache (bigger lines = smaller buffers). Also, along these translation buffers there are bits that stores if the line was modified, and how often/lately was accessed. Code and data locality are advantageous in having big lines of cache. However, cache lines must be small enough so a write/read of the cache line will be fast.
A four-way set associative cache can store a memory location in any one of four cache lines. So, you get one fourth of the cache, and it will be 4k or 2^12 bytes. You then just take the last 12 bits of the address and those show the address in cache. Add to that 4k, 8k and 12k.

But you should really start studying (as what I saw could be very well wrong)