do you think amd can do what intel does? create longer pipelines and scale clocks higher?
- Thread starter AkumaX
- Start date
can they technically, sure, i don't think it's that hard to break up the steps...
would they? probably not... their issue isn't really speed, it's marketing
(everybody who is not a computer dork looks for "Intel Inside")
plus now the've got it in good with people who know computers who know their products are technically better
would they? probably not... their issue isn't really speed, it's marketing
(everybody who is not a computer dork looks for "Intel Inside")
plus now the've got it in good with people who know computers who know their products are technically better
Jeff7181
Lifer
- Aug 21, 2002
- 18,368
- 11
- 81
Of course... they could probably make one with a 60 stage pipeline (twice as long as the Prescott) if they felt like it. But AMD's method has been to use a shorter pipeline and do more operations per clock cycle. Intel uses a longer pipeline that does less instructions per clock cycle, but it runs at a faster speed so the operations per second are almost the same. Because of the longer pipeline, Intel needs a VERY good branch predictor to keep the pipeline as full as possible so it's not sitting there idle.
*EDIT* Think of an AMD processor as a 4 lane highway with a speed limit of 55 mph, and a Pentium 4 as a 3 lane highway with a speed limit of 70 mph. They both move almost exactly the same number of cars in a given time period, but... to further stretch this analogy... if you have lots of cars entering and exiting the highway, having 4 lanes moving at 55 mph will be more beneficial than 3 lanes at 70 mph. The 3 lane highway will need longer and better entrance and exit ramps (brand predictors) to get cars onto and off from the highway efficiently without slowing down traffic.
*EDIT* Think of an AMD processor as a 4 lane highway with a speed limit of 55 mph, and a Pentium 4 as a 3 lane highway with a speed limit of 70 mph. They both move almost exactly the same number of cars in a given time period, but... to further stretch this analogy... if you have lots of cars entering and exiting the highway, having 4 lanes moving at 55 mph will be more beneficial than 3 lanes at 70 mph. The 3 lane highway will need longer and better entrance and exit ramps (brand predictors) to get cars onto and off from the highway efficiently without slowing down traffic.
A very good, old article about why AMD uses short pipelines.
In a nutshell, part because of R&D and part acquisition, AMD owns a branch predictor design that can be considered anywhere from good to great. It's first debut was on the K6.
In a nutshell, part because of R&D and part acquisition, AMD owns a branch predictor design that can be considered anywhere from good to great. It's first debut was on the K6.
With shorter pipelines, branch prediction isn't as necessary (because starting over isn't as onerous.) Whereas on the new prescot, branch prediction is very important because a wrong turn means a lot more back tracking then in an amd.
I'm having trouble finding definitive evidence, but I was under the impression that the K6 had the most accurate branch predictor in the x86 world.
I'm gonna go out on a limb and suggest that Prescott's branch predictor unit might be better than the K6's. If I remember correctly, it's either tournament or cascade (or I'm confused with Alpha) and it's even got indirect branch prediction (so I hear). The k6, on the other hand, used a two-level predictor scheme which I think was first published back in 1988.
As for the pipelininig, it's actually a lot harder than simply dividing stages. Intel hand-tunes every single microarchitecture and for good reason. High clocks are a pain. AMD is more likely to lack the resources or the time to do long pipelines.
As for the pipelininig, it's actually a lot harder than simply dividing stages. Intel hand-tunes every single microarchitecture and for good reason. High clocks are a pain. AMD is more likely to lack the resources or the time to do long pipelines.
The impressive thing about Intel lengthening the pipeline, is the fact that performance remains high. If you were to only add more stages to the pipeline without other significant architectural improvements, you'd get a significantly poorer performer.
The fact that Intel has done this with Prescott, and yet it performs similar to a Northwood is really quite impressive.
So, could AMD add more stages to the pipeline to help ramp up clockspeed? Sure. The question should be if they could they do so without taking a huge performance hit?
The fact that Intel has done this with Prescott, and yet it performs similar to a Northwood is really quite impressive.
So, could AMD add more stages to the pipeline to help ramp up clockspeed? Sure. The question should be if they could they do so without taking a huge performance hit?
Yeah, among other things. Anand's Prescott article has an excellent write-up of what makes the deeper pipeline work.
Like I said, read Anand's Prescott article. He did an outstanding job (as usual) of explaining pipelines to the masses.
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