Digital Logic Problem Statement

[GodLovesPunk]

I'm an electronics engineering undergraduate student at the University of North Texas. I'm taking a class called Digital Logic and we have a semester project. We use Altera Quartus II software. The problem statement is this:

"Using state machine design, input two BCD numbers from switches (on the Altera DE2 board we use), add the two numbers and display the result on the seven segment display. A reset button restarts the state machine to the beginning. Incorporate a state machine that advances states based on a momentary push-button switch input. Test the inputs for validity and display E for error if a non-valid BCD number is entered."

Now I understand the material well, but we've never had a problem like this. Typically the labs are fairly simple and include in depth guidelines. The instructor and TAs are not able to help us; its driving me crazy! Thought I'd take a shot in the dark and see if anyone is somewhat knowledgeable or an expert in digital logic and VHDL. Thanks guys!

 

[PottedMeat]

That doesn't seem too hard. You could scribble a simple solution together on paper.

We need to know how many inputs you have. Inputs: Bits in input 1, input 2, reset, clock. Outputs: 7.

I would do the following:
1. Make a chart of all the possible inputs and outputs. For each pair of inputs, you need to translate that into 7 bits - one for each segment. For example 2 + 3 = 5, so 0b00000010 + 0b00000011 -> Segments a,f,g,c,d ( however thats mapped on the logic array )
2. Draw a state machine representation - I think you just use the output state-> 0,1,2,3,4,5,6,7,8,9,E dependent on the states of the 2 inputs, reset, and clock. Basically a sketch of circles and arrows looping back on one another. Like if you send a clock pulse, but the inputs haven't changed, you loop back to that state. Hmm I don't know what the initial state would be, maybe a blank display?
3. I don't know VHDL, My brother did this sort of thing in his CS class, but it seems like you could do this really easily with a lookup table.

 

[degibson]

I don't remember enough VHDL to be helpful with syntax, but PottedMeat's suggestions are basically right-on as far as how to go about the work.

Just remember: think modular. Break the problem into easily-solved pieces. A BCD to 7-Segment translator, for instance (I fondly remember making one of those myself). Don't forget about the 'E' state.