[Digital Foundry] Radeon RDNA vs GCN

NTMBK

Diamond Member
Nov 14, 2011
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https://www.eurogamer.net/articles/digitalfoundry-2019-teraflop-face-off-current-gen-vs-next-gen

Quite an interesting article, trying to normalise FLOPs and bandwidth and then compare across generations to see how performance has improved. I think Richard's analysis of the DX12 results is missing one crucial thing- the original GCN1 parts like Tahiti did not have many async compute engines, whereas the consoles had significantly more beefed up async capabilities,which were then brought back to PC from Hawaii onwards. I think it would have been very interesting to have a Tonga part compared against Tahiti (with normalised bandwidth and clocks), to see how their DX12 performance compared.
 

Guru

Senior member
May 5, 2017
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Cool. Navi seems like the real deal, primed to take on Nvidia hardware
 

beginner99

Diamond Member
Jun 2, 2009
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The problem here is they are comparing CU to CU. But there obviously are large differences between CU of gcn1 vs navi especially !!! also in die space needed (cache). This is essential the same as with Apple cores. Apple custom ARM cores are pretty large (AFAIK larger than skylake cores) hence no wonder they have higher IPC. This works fine if all your newest cores go into +$700 iphones. intel on the otherhand has to sell the same core in $300 cheapo laptops. Hence die space usage matters.
Main point being most of these comparison simply ignore this even if it certainly affects a design and is relevant for pricing the product and is also a form of efficiency. A slower clocked large/wide core will always be more efficient at cost of silicon usage.
 

GodisanAtheist

Golden Member
Nov 16, 2006
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The problem here is they are comparing CU to CU. But there obviously are large differences between CU of gcn1 vs navi especially !!! also in die space needed (cache). This is essential the same as with Apple cores. Apple custom ARM cores are pretty large (AFAIK larger than skylake cores) hence no wonder they have higher IPC. This works fine if all your newest cores go into +$700 iphones. intel on the otherhand has to sell the same core in $300 cheapo laptops. Hence die space usage matters.
Main point being most of these comparison simply ignore this even if it certainly affects a design and is relevant for pricing the product and is also a form of efficiency. A slower clocked large/wide core will always be more efficient at cost of silicon usage.
- Agreed, these articles always fall a bit flat because there really is no good way most of the time to isolate all the way down. This type of article needs to be paired with a deep dive so not only can we see scaleing from cu to cu, but all get the theory behind why there is an improvement in scaling as well (is it just clocks, caches, was some bottleneck removed, was some secret sauce sprinkled in?).

Looks like its all phone reviews all the time on AT now :confused_old:
 

Mopetar

Diamond Member
Jan 31, 2011
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Main point being most of these comparison simply ignore this even if it certainly affects a design and is relevant for pricing the product and is also a form of efficiency. A slower clocked large/wide core will always be more efficient at cost of silicon usage.
I don't think cores getting larger is too unfair. In some ways it's almost desirable too add a few extra shortcuts at the cost of more silicon in order to spread the heat out. If we did nothing but die shrinks, or even aimed at reducing the transistor budget per core (assuming performance neutral results) we'd hit a problem with the newer nodes having everything packed too densely. The added silicon to the cores give an opportunity for other parts to go dormant on occasion and to spread the heat around a little bit more.

From an end-user perspective, the architectural changes don't matter at all. The best measurement of progress is always performance per dollar.
 

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