Differential latch question - polarity of input - outputs

[pX]

OK, look at the rip of this picture from a journal article I was reading:
pic here
Isn't the polarity for IN and OUT supposed to be reversed? If you plug some 1s and 0s into the circuit OUT and OUT* should be reversed, right? Maybe I am going crazy, but I have stared at this diff latch for 10 minutes to no avail.

 

[TuxDave]

You're right. Unless this is supposed to be an inverting latch, then the Out' and Out are mixed up. For the pmos in the p-latch and nmos in the n-latch... what's that little * next to the transistor supposed to mean from the paper?

 

[pX]

* is supposed to mean "weak" in the paper

thanks!

 

[TuxDave]

Just curious, but what is the title of the paper that you're reading?

 

[SuperTool]

If * means weak, it's wrong. In the n-latch, the pmos should be weak for writeability, but the star is next to the nmos. Vice-versa for p-latch.

 

[TuxDave]

Originally posted by: SuperTool
If * means weak, it's wrong. In the n-latch, the pmos should be weak for writeability, but the star is next to the nmos. Vice-versa for p-latch.

It's so strange that one paper can have so many errors. I want to see the paper to see what's going on.

 

[SuperTool]

Originally posted by: TuxDave

Originally posted by: SuperTool
If * means weak, it's wrong. In the n-latch, the pmos should be weak for writeability, but the star is next to the nmos. Vice-versa for p-latch.

It's so strange that one paper can have so many errors. I want to see the paper to see what's going on.

I guess the nmos can be weak too, but the pmos must be weak for writeability.

 

[TuxDave]

Originally posted by: SuperTool

Originally posted by: TuxDave

Originally posted by: SuperTool
If * means weak, it's wrong. In the n-latch, the pmos should be weak for writeability, but the star is next to the nmos. Vice-versa for p-latch.

It's so strange that one paper can have so many errors. I want to see the paper to see what's going on.

I guess the nmos can be weak too, but the pmos must be weak for writeability.

I agree. The access transistor should be stronger than the pmos in the n-latch configuration and you will switch faster if the pmos was stronger than the pull down nmos.

 

[SuperTool]

Originally posted by: TuxDave

Originally posted by: SuperTool

Originally posted by: TuxDave

Originally posted by: SuperTool
If * means weak, it's wrong. In the n-latch, the pmos should be weak for writeability, but the star is next to the nmos. Vice-versa for p-latch.

It's so strange that one paper can have so many errors. I want to see the paper to see what's going on.

I guess the nmos can be weak too, but the pmos must be weak for writeability.

I agree. The access transistor should be stronger than the pmos in the n-latch configuration and you will switch faster if the pmos was stronger than the pull down nmos.

That's what I don't like about these latches. You have to size the pmos small for writeability, but then that makes the rising transition very slow. Also, you should not drive a big load or wire without buffering the outputs first with this kind of latch because it'll be slow and noise sensitive.

 

[pX]

the writers are some big names, well sort of, they 'invented' the TSPC flipflop

found a copy of it here


figures 5, 6, and 7 are the ones I think are labeled wrong.