Did Intel's DC chipset make an 8-way FSB likely for future P4's?

[MadRat]

I'm thinking that Intel's 800MHz front-side bus will actually be eight separate 100MHz channels. Does anyone really think it will be four-way 200MHz? Seriously, Intel has already had delay after delay in the original speed bump from a four-way 100MHz to four-way 133MHz front-side bus, why would a 200MHz front-sdie bus suddenly become so easy?

 

[Lord Evermore]

delay after delay? It wasn't THAT long between them, and they didn't NEED to come out with it any faster. I'd bet on Intel getting a 200MHz quad-pumped bus before I'd bet on AMD coming up with a stable 200MHz double-pumped bus. I like AMD, but they aren't keeping up with frequencies, plain and simple.

No way it'll be eight 100MHz busses. For one thing, if you used that as the way to make "8-way" systems, then it'd mean each processor was limited to 100MHz bus, which you can guess would be extremely limited. Even with several processors sharing an 800MHz bus, because each one wouldn't need it constantly, each processor would get more than just a 1/8th share of the bandwidth at any particular moment.

Second, it'd be an entirely different design than anything else Intel has ever done, so I doubt they'd make such a change while still using the same processor. Even if you considered it as still eight 100MHz shared busses (separate channels but all accessible by every processor) it'd still be vastly different than the AGTL+ bus they use now. Keep in mind that GTL has evolved and been used in every Intel Pentium processor since the Pentium Pro.

Intel's "delays" are because Intel won't release anything until they're absolutely positively sure it's going to be stable and not cause any issues like excessive EMI or incompatibility (they learned from the i820 and the MTH).

 

[SexyK]

I'd be willing to bet the farm its a quad pumped 200MHz bus. I don't know if there is technology out there right now that can send data 8 times a clock:Q!

Kramer

 

[Lord Evermore]

Actually someone is working on it. I can't remember who right now though.

I vote for a brand name change to "Octanium" if they ever switch to a 8x bus. 🙂 It sounds silly, but no worse than Pentium, and at least "Octane" implies power.

 

[MadRat]

The delays were associated with RDRAM but they go to show the technical challenges when you increase speeds. Increasing the number of pathways would be a more logical route, think double-pumped QDR.

 

[Lord Evermore]

"double pumped" is the term people use to indicate double data rate... 🙂

I just don't think having multiple separate channels to the chipset is something Intel would try to do (and even if they did, no way are they going to steal from their Xeon sales by making the P4 SMP capable; that's the only thing the Xeon line really has to compete; at least in each "version" change of the Pentium line the Xeon doesn't have any cache advantage).

The 760MP/MPX chipsets from AMD have multiple channels to the chipset, but they're also to separate processors. In order to make an "800MHz" bus by combining two 400MHz QDR busses, Intel would likely have to go through a LOT of changes that they might not be able to do without changing everything else about the chipset design, since they would be "bonded" busses that all go to the same processor. There'd have to be logic integrated into the processor and the chipset to control data flow balancing across the two channels (which of course they do now with dual-channel memory, but that doesn't mean they can just slap it together for the processor). And then of course, would they make ALL P4's capable of the "two channel" connection? Or disable it in a "cheap" version, which might be more expensive to make than it's worth (disabling Hyperthreading in the P4 all this time was more cost-effective than designing a non-HT version, but that might not be the same with a two-channel version).