Determining FSB hole patterns

[Rubycon]

Is this unique to motherboards or chipsets? What I mean is if a certain FSB (or BCLK) does NOT work on brand A X58 would that same anomaly exist on brand B as well?

Someone should start a database. Folks using unlocked processors could benefit the most.

 

[DominionSeraph]

Not all of us have the American taxpayer to pay for air conditioning and replacement processors. Such holes are pretty much meaningless for long-term stable non-blast furnace overclocks.

 

[DrMrLordX]

Is this unique to motherboards or chipsets? What I mean is if a certain FSB (or BCLK) does NOT work on brand A X58 would that same anomaly exist on brand B as well?

Someone should start a database. Folks using unlocked processors could benefit the most.

From what I've seen, this appears to be a function of a). the memory controller and b). the memory controller's implementation. I haven't learned anywhere near all that there is to learn about FSB holes, but when they first started showing up (or getting noticed) back in the Core 2 days, it was all related to memory straps, and all that crap had to do with the memory controller.

BCLK holes on x58 and Lynnfield-equipped P55/H57/H55 are an unknown to me, though when it comes to Clarksdale, it would come as no surprise to me if BCLK holes are effectively created by the 45nm memory controller that it uses (which reportedly is an adaptation of a memory controller from the Penryn days).

Not all of us have the American taxpayer to pay for air conditioning and replacement processors. Such holes are pretty much meaningless for long-term stable non-blast furnace overclocks.

Meh? Cmon, it still merits discussion.

 

[Rubycon]

Not all of us have the American taxpayer to pay for air conditioning and replacement processors. Such holes are pretty much meaningless for long-term stable non-blast furnace overclocks.

I don't pay taxes and am not an American citizen.

From what I've seen, this appears to be a function of a). the memory controller and b). the memory controller's implementation. I haven't learned anywhere near all that there is to learn about FSB holes, but when they first started showing up (or getting noticed) back in the Core 2 days, it was all related to memory straps, and all that crap had to do with the memory controller.

BCLK holes on x58 and Lynnfield-equipped P55/H57/H55 are an unknown to me, though when it comes to Clarksdale, it would come as no surprise to me if BCLK holes are effectively created by the 45nm memory controller that it uses (which reportedly is an adaptation of a memory controller from the Penryn days).

I'm seeing it more with silly Gulftown CPUs. Probably exists with i7 quads too but honestly I never really messed around with 965/975s a whole lot because my W3520 overclocked better!

 

[aigomorla]

from my experience it has to do with board + ram + cpu.

So if you change 1, you will offset your fsb hole.

 

[Rubycon]

from my experience it has to do with board + ram + cpu.

So if you change 1, you will offset your fsb hole.

It's worse than a 5x5 rubik's cube now!

 

[aigomorla]

It's worse than a 5x5 rubik's cube now!

yeah...

but the holes on gulftown is more explained on the poor MC.

Gulftown just does not like a high blck nor a high uniclock.

 

[Rubycon]

yeah...

but the holes on gulftown is more explained on the poor MC.

Gulftown just does not like a high blck nor a high uniclock.

Haha I have them both fairly high. 208 BCLK and ~3600 uncore.

The 49 BIOS (Classified 762) does not properly recognize the 1.5X (vs. 2X) requirement of RAM speed for uncore. Auto is most likely running at 1.5X but quite a bit slower too. At just under 4.4GHz my Cinebench 11.5 scores are close to 11.5. Not bad! On AIR to boot!

 

[aigomorla]

thats nothing compared to a 32nm X5677 :X

 

[Rubycon]

thats nothing compared to a 32nm X5677 :X

Well considering in some memory intensive tasks the 980X is trailing my 3520 I'm duly unimpressed. I wish they had 8 cores TBH. Or at least 5GHz on air was the new 4GHz.

Overall for the same (list) price of the 975 it's OK. Of course you can get 975s now for $799 at microcenter. (Still a W3520 is/was better) Early batch from nearly a year ago when D0s were the talk completely destroys every other 1366 CPU I had in my hands (about 40 in all). The 980Xs are not bad HOWEVER I find that they are VERY close OC wise within 100MHz of each other. If you really use every single core in multithreaded apps even 50MHz does make a difference you can see almost immediately.

 

[DrMrLordX]

I'm seeing it more with silly Gulftown CPUs. Probably exists with i7 quads too but honestly I never really messed around with 965/975s a whole lot because my W3520 overclocked better!

Hmm, the plot thickens.

Have you done any memory bandwidth and latency benchmarks on both sides of a BCLK hole?

 

[Rubycon]

Hmm, the plot thickens.

Have you done any memory bandwidth and latency benchmarks on both sides of a BCLK hole?

No I have not although most benchmark runs vary enough to negate the significant difference.

 

[aigomorla]

im waiting for someone to pop a 980X.

:X

I might get lucky and have a X5677 to play with.
If that goes well, ima shoot for 250+ Bclk!

 

[Rubycon]

im waiting for someone to pop a 980X.

:X

I might get lucky and have a X5677 to play with.
If that goes well, ima shoot for 250+ Bclk!

Good luck with that. Never possible here with 12 or 24GB running at 1T!

Whose going to pop theirs?

These chips can take a lot like balloons! Just when it pops it's too late!

 

[DrMrLordX]

No I have not although most benchmark runs vary enough to negate the significant difference.

Well, the thing is, on Core 2/FSB boards, often times the the memory bandwidth would drop off precipitously on the high side of an FSB hole, which seemed to indicate that the memory controller was switching straps or something or other. It would be interesting to see if such a drop occurred on the high side of a BCLK hole on an X58 system (Gulftown or otherwise).

 

[Rubycon]

Yes the strap changeover, no these were not around straps.
Memory benchmarks show this well.

 

[BTRY B 529th FA BN]

My crazy theory is it's how the memory maker designs the sticks like the trace routes.

 

[PsiStar]

I have been thinking thru my opinion as it is all I have at the moment, there is a great deal about this that I do not understand. I work in related areas, BUT this only creates more questions & not necessarily an educated opinion!

However, I feel that I experienced this with my ASUS P6X58D. I feel that I hit a limit at 190. After a couple of frustrating hours, then I had a little wine & said WTF, I bumped it up to 205 & had success! Currently have been stable (as any Dell!) at 210 for hours & days of maxxed number-crunching.

So .. this question is "why"? Is it the RAM or the m/b? How do you figure out which?

 

[BTRY B 529th FA BN]

I think it is related to the RAM.

 

[Rubycon]

I think it is related to the RAM.

RAM, IMC, board ground planes, you name it - they all interact. Remember they were designed around a 133MHz base clock!

 

[PsiStar]

rubycon gets it, but I think that there is a logical way to deduce what is causing the hole with the info that we know now. Eludes me ... ... ..

I am about to upgrade another system ... as in gut it & put in all new stuff probably around the i7 980x. With that, I will probably buy some RAM with higher spec than what is currently in dogbert (the i7 920 system in the signature). I'll try this new RAM in dogbert to see if this hole changes perceptibly. I don't expect it to.

This is one way that might eliminate 1 variable.

Of course I am thinking about getting a ASUS Rampage III Extreme instead of the same m/b, which introduces a new variable but could also allow experimenting with a newer designed board in the same way. The EVGA Classified SR-2 is pretty interesting tho if things explode in a good way, that would be the path. It supposedly allows OC & would be interesting to know if the hole exists with it.

 

[BTRY B 529th FA BN]

vote sticky

 

[Ben90]

Maybe if we could gather some actual information about our "strap" problem it would be worth a look for others to read. Much better than the thousands of: "Which CPU to get" threads.

Can Ruby and Aigo comment on if the IMC does indeed throttle any part of the memory subsystem when coming out of the high side of the Bclock holes? I think Ruby answered my question in post #16, but I'm a little confused on the wording of it