Dell, IBM give thumbs up to ARM servers

[cbn]

http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=224900076

In other articles I have seen ARM A9 cores @ 2Ghz mentioned for file and webservers.

How does that compare to Intel's Atom? Is there a standardized test useful for comparing x86 to non-x86?

 

[ElFenix]

wtf when did dell move beyond screwing stuff together and actually start leading things?

they ship via servers?!

 

[cbn]

wtf when did dell move beyond screwing stuff together and actually start leading things?

they ship via servers?!

I couldn't find any more information on Dell and ARM server, but here is another company that wants to use the technology.

http://www.smooth-stone.com/


This also sounds pretty interesting. 3D stacking of DRAM?

This research project will investigate the use of the ARM® Cortex™-A9 MPCore™ multicore processor along with 3D DRAM structures and packaging technology to enable the building of dense, cost-effective and green data centers through “good enough” nodes of processor performance and high-bandwidth access to server memory.

“Server workloads are primarily memory-bound and typically benefit little from complex computational capabilities. Embedded-like processors with 3D DRAM are the most effective approach to executing these workloads in energy-constrained environments. It is finally time to put the embedded system into data centers to enable energy scalability,” said Professor Babak Falsafi, the Director of Parallel Systems Architecture Lab at EPFL.

 

[cbn]

http://www.computer.org/portal/web/csdl/doi/10.1109/MICRO.2006.18

3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact.

Can someone explain how this increase in "memory bandwidth" is actually occurring? The abstract here seems to be talking about 3D DRAM being used as "cache".

 

[DrMrLordX]

Can someone explain how this increase in "memory bandwidth" is actually occurring? The abstract here seems to be talking about 3D DRAM being used as "cache".

My way of thinking may be a tad simplistic, but I have always been under the impression that reducing the physical distance between two (or more) ICs would reduce the power and hardware needed to facilitate communication between said ICs. Moving your DRAM to within several micrometers of your memory controller should make everything faster within the same power envelope (it should also make everything require less power within the same performance envelope).