- Dec 25, 2013
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Peculiar: Intel to switch to HD SRAM cells at 10nm for Core, from HP
EDIT: My theory has been debunked. Credits to Mux for a good catch. I thought Intel has only published two cell sizes for 14nm.
Additional cell sizes
Intel
14nm HP: 0.0588µm²
14nm HD: 0.0499µm²
Samsung
10nm HP: 0.049µm²
10nm HD: 0.040µm²
TSMC
16nm HD: 0.070µm²
7nm HD: 0.027µm²
Background
I already knew that Intel's 10nm high-density (HD) SRAM size had shrunk only 1.6x. But while going over the SRAM sizes that Intel provided at their March 28 Manufacturing Day, I noticed how especially the high-performance (HP) cell seemed to fell way above the trendline, verified with a ruler. This was confirmed with a quick calculation that showed Intel had only shrunk its size by 1.33x. This, frankly, made me suspicious.
Now, if you've remembered -- or Intel wanted you to remember -- anything about their mfg day, it was that they had achieve a 2.7x transistor density increase by using some Hyperscaling techniques (notably, the use of self-aligned quad patterning, single dummy FinFET gates and contact over active gate), which is significantly more than Moore's Law, which would offset the slower cadence and keep Moore's Law alive, especially the cost per transistor reduction part of it.
So I was baffled when my calculator showed SRAM had shrunk only 1.33x. In general, from the start I had been disappointed by the SRAM. TSMC only shares the size of their HD cells, and for 7nm it came in at 0.027µm². I had squarely expected that Intel would beat that number, but their 0.0312µm² size clearly left much to be desired.
As I noted in my tweet before I delved deeper, Intel's 10nm SRAM seems comparable to other's 10nm, while Intel had wanted to let everybody at the mfg day know that its 10nm was comparable to other's 7nm.
As can be seen in the picture above, the trendline is about 0.54x (this was the HP scaling from 22nm to 14nm), which is 1.85x. Another thing to know is that the HD size is purely mentioned for bragging rights, since they are hardly used given their poor performance, so one should normally look for HP numbers.
Analysis
Now, given that Intel has been leading the semiconductor manufacturing industry for more than 15 years now, one should should normally assume that Intel has smart engineers that make smart decisions. So the question remains: what went through those engineers' heads when they decided that the point for their 10nm HP cell, which will go into HVM 3.5 years after 14nm, would be only 1.33x below 14nm?
Even for the HD cell size there should be no question vs. TSMC 7nm: their metal pitch is lower at 36nm vs. 40nm (although I have been told metal pitch does not matter for SRAM size) and gate pitch is the same. Even accounting for the fact that Intel uses a 7.5 track library vs. TSMC's 6 track one, it's larger than it should be.
Now, all fine and good, we know that SRAM is more difficult to scale than logic without losing performance and reliability. So maybe they just couldn't make it smaller given that they aren't doing very tall aspect ratio fins (Intel 10nm is about 8:1 vs. TSMC 7nm ">10:1"), or other innovations besides the Hyperscaling ones.
But this is ignoring a real life data point that Intel gave. Intel says a typical die at 10nm will become 0.43x as big.
So if SRAM only becomes 25% smaller, this seems to make it quite difficult for a die to become that much smaller given that it makes up a non-negligible portion of an IC.
So my immediate instinct was to compare the 10nm HD cell vs. 10nm HP.
If you do this, you get 0.0588µm² / 0.0312µm², which is 1.88x. So 10nm HD is 0.53x the 14nm HP size. Well, this seems very close to the 0.54x shrink from 22->14nm. Coincidence? I don't think so.
This led me to the hypothesis that Intel will switch from using high-performance SRAM cells like they have always done, to using high-density cells.
How to prove this?
Well, if we knew just how much the IO, logic and SRAM cells scale -- and how much they make up in this simplified model in the above picture, then we could calculate how much the shrink will be and see if it matches the 0.43x scaling. However, since we have no clue about IO, what we can do instead is calculate how much the IO would have to shrink to match the 0.43x number with a given SRAM scaling. (We know that logic scales by 0.37x.)
So first, what weights does Intel use to get those numbers? Fortunately, Intel had provided those in the 14nm talk.
Now the task is really straightforward. We can use the provided numbers to make the table for 10nm. I have made two tables: one where I use the 1.33x HP scaling (due to errata on my part 1.25x in the table), and one where I use the 1.88x HP->HD value.
In this microprocessor model, logic makes up 60% of the die and becomes 37% the size from 14->10, for a 0.222 area contribution of the 10nm (0.6*0.37) die. Now if you assume SRAM scales by 25% (I made a typo but it doesn't matter), you get nonsense. Intel would have to scale IO 0.14x (correct number) to get a sum of 0.43. This clearly ain't gonna happen.
Now, maybe Intel secretly used the HD cells to get those numbers, but let's first look at the HP->HD calculation to see if we need to consider that possibility.
If you do the math, this model dictates that Intel has shrunk IO by 0.50x. Even this already seems a lot given that IO shrunk only 0.6x at 14nm, so even more is simply implausible.
Lastly, for reference here is what actual weightings are for Intel and Apple dies.
Conclusion
To recap, the fundamental problem here is that Intel choose to make its high-density SRAM only 1.33x smaller, which goes right in the face of everything they told about Hyperscaling to improve weighted transistor density by 2.3x and logic density by 2.7x. Not to mention their claimed 3 year advantage: Samsung's 10nm will be available at the end of this month.
Using only data Intel gave at Manufacturing Day (and the 14nm SRAM sizes earlier disclosed), one finds that in order to match the claimed 0.43x weighted processor scaling, the most plausible assumption one has to make it that Intel has switched from using high-performance SRAM cells to using high-density cells at 10nm. Otherwise, one would have to assume that Intel scaled the IO by 0.39x or even more, which is absurd.
By switching from HP to HD cells, Intel can maintain their historical 0.53x SRAM scaling. Indeed, what I would even argue is that Intel intentionally relaxed the scaling of their SRAM cells to not degrade their performance too much, so to make HD cells usable for commercial use, instead of solely for bragging rights (Cf. TSMC 7nm -- although you may happily correct me if I'm wrong and those HD cells are used by Apple, Qualcomm, Nvidia, etc., but I remember Kanter saying otherwise).
I wonder if Intel Custom Foundry had any influence in the decisions for the SRAM size definitions.
To me that seems the most plausible explanation for the poor SRAM scaling. Feel free to share your thoughts and opinions.
EDIT: My theory has been debunked. Credits to Mux for a good catch. I thought Intel has only published two cell sizes for 14nm.
Additional cell sizes
Intel
14nm HP: 0.0588µm²
14nm HD: 0.0499µm²
Samsung
10nm HP: 0.049µm²
10nm HD: 0.040µm²
TSMC
16nm HD: 0.070µm²
7nm HD: 0.027µm²
Background
I already knew that Intel's 10nm high-density (HD) SRAM size had shrunk only 1.6x. But while going over the SRAM sizes that Intel provided at their March 28 Manufacturing Day, I noticed how especially the high-performance (HP) cell seemed to fell way above the trendline, verified with a ruler. This was confirmed with a quick calculation that showed Intel had only shrunk its size by 1.33x. This, frankly, made me suspicious.
Now, if you've remembered -- or Intel wanted you to remember -- anything about their mfg day, it was that they had achieve a 2.7x transistor density increase by using some Hyperscaling techniques (notably, the use of self-aligned quad patterning, single dummy FinFET gates and contact over active gate), which is significantly more than Moore's Law, which would offset the slower cadence and keep Moore's Law alive, especially the cost per transistor reduction part of it.
So I was baffled when my calculator showed SRAM had shrunk only 1.33x. In general, from the start I had been disappointed by the SRAM. TSMC only shares the size of their HD cells, and for 7nm it came in at 0.027µm². I had squarely expected that Intel would beat that number, but their 0.0312µm² size clearly left much to be desired.
As I noted in my tweet before I delved deeper, Intel's 10nm SRAM seems comparable to other's 10nm, while Intel had wanted to let everybody at the mfg day know that its 10nm was comparable to other's 7nm.
As can be seen in the picture above, the trendline is about 0.54x (this was the HP scaling from 22nm to 14nm), which is 1.85x. Another thing to know is that the HD size is purely mentioned for bragging rights, since they are hardly used given their poor performance, so one should normally look for HP numbers.
Analysis
Now, given that Intel has been leading the semiconductor manufacturing industry for more than 15 years now, one should should normally assume that Intel has smart engineers that make smart decisions. So the question remains: what went through those engineers' heads when they decided that the point for their 10nm HP cell, which will go into HVM 3.5 years after 14nm, would be only 1.33x below 14nm?
Even for the HD cell size there should be no question vs. TSMC 7nm: their metal pitch is lower at 36nm vs. 40nm (although I have been told metal pitch does not matter for SRAM size) and gate pitch is the same. Even accounting for the fact that Intel uses a 7.5 track library vs. TSMC's 6 track one, it's larger than it should be.
Now, all fine and good, we know that SRAM is more difficult to scale than logic without losing performance and reliability. So maybe they just couldn't make it smaller given that they aren't doing very tall aspect ratio fins (Intel 10nm is about 8:1 vs. TSMC 7nm ">10:1"), or other innovations besides the Hyperscaling ones.
But this is ignoring a real life data point that Intel gave. Intel says a typical die at 10nm will become 0.43x as big.
So if SRAM only becomes 25% smaller, this seems to make it quite difficult for a die to become that much smaller given that it makes up a non-negligible portion of an IC.
So my immediate instinct was to compare the 10nm HD cell vs. 10nm HP.
If you do this, you get 0.0588µm² / 0.0312µm², which is 1.88x. So 10nm HD is 0.53x the 14nm HP size. Well, this seems very close to the 0.54x shrink from 22->14nm. Coincidence? I don't think so.
This led me to the hypothesis that Intel will switch from using high-performance SRAM cells like they have always done, to using high-density cells.
How to prove this?
Well, if we knew just how much the IO, logic and SRAM cells scale -- and how much they make up in this simplified model in the above picture, then we could calculate how much the shrink will be and see if it matches the 0.43x scaling. However, since we have no clue about IO, what we can do instead is calculate how much the IO would have to shrink to match the 0.43x number with a given SRAM scaling. (We know that logic scales by 0.37x.)
So first, what weights does Intel use to get those numbers? Fortunately, Intel had provided those in the 14nm talk.
Now the task is really straightforward. We can use the provided numbers to make the table for 10nm. I have made two tables: one where I use the 1.33x HP scaling (due to errata on my part 1.25x in the table), and one where I use the 1.88x HP->HD value.
In this microprocessor model, logic makes up 60% of the die and becomes 37% the size from 14->10, for a 0.222 area contribution of the 10nm (0.6*0.37) die. Now if you assume SRAM scales by 25% (I made a typo but it doesn't matter), you get nonsense. Intel would have to scale IO 0.14x (correct number) to get a sum of 0.43. This clearly ain't gonna happen.
Now, maybe Intel secretly used the HD cells to get those numbers, but let's first look at the HP->HD calculation to see if we need to consider that possibility.
If you do the math, this model dictates that Intel has shrunk IO by 0.50x. Even this already seems a lot given that IO shrunk only 0.6x at 14nm, so even more is simply implausible.
Lastly, for reference here is what actual weightings are for Intel and Apple dies.
Conclusion
To recap, the fundamental problem here is that Intel choose to make its high-density SRAM only 1.33x smaller, which goes right in the face of everything they told about Hyperscaling to improve weighted transistor density by 2.3x and logic density by 2.7x. Not to mention their claimed 3 year advantage: Samsung's 10nm will be available at the end of this month.
Using only data Intel gave at Manufacturing Day (and the 14nm SRAM sizes earlier disclosed), one finds that in order to match the claimed 0.43x weighted processor scaling, the most plausible assumption one has to make it that Intel has switched from using high-performance SRAM cells to using high-density cells at 10nm. Otherwise, one would have to assume that Intel scaled the IO by 0.39x or even more, which is absurd.
By switching from HP to HD cells, Intel can maintain their historical 0.53x SRAM scaling. Indeed, what I would even argue is that Intel intentionally relaxed the scaling of their SRAM cells to not degrade their performance too much, so to make HD cells usable for commercial use, instead of solely for bragging rights (Cf. TSMC 7nm -- although you may happily correct me if I'm wrong and those HD cells are used by Apple, Qualcomm, Nvidia, etc., but I remember Kanter saying otherwise).
I wonder if Intel Custom Foundry had any influence in the decisions for the SRAM size definitions.
To me that seems the most plausible explanation for the poor SRAM scaling. Feel free to share your thoughts and opinions.
Last edited:
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