Question DDR4 channels vs DDR5 subchannels

[Executor_]

In a system with dual-channel DDR4, the memory controller can send out two reads simultaneously.
With quad-channel DDR4, that goes up to four simultaneous reads.

DDR5 has two subchannels per channel. Does that mean the memory controller can have twice as many reads in-flight at the same time? ie. does dual-channel DDR5 (so 4 subchannels total) mean four simultaneous reads?

 

[Hotrod2go]

"Each DDR5 DIMM has two independent channels. Earlier DIMM generations featured only a single channel and one CA (Command/Address) bus controlling the whole memory module with its 64 (for non-ECC) or 72 (for ECC) data lines. Both subchannels on a DDR5 DIMM each have their own CA bus, controlling 32 bits for non-ECC memory and either 36 or 40 data lines for ECC memory, resulting in a total number of either 64, 72 or 80 data lines. The reduced bus width is compensated by a doubled minimum burst length of 16, which preserves the minimum access size of 64 bytes, which matches the cache line size used by modern x86 microprocessors."

DDR5 SDRAM - Wikipedia

en.wikipedia.org

Your welcome. 🙂