Not an expert but from my understanding
The memory has as an underlying latency requirement in seconds. Usually this is not known but can be estimated from known working CAS and clock pairings.
CAS latency is specified in units of cycles e.g. CAS 7 means 7 cycles.
The effective time delay in seconds for a specific CAS latency depends on the clock speed of the memory i.e. effective delay = (CAS delay)/(clock speed) = (CAS delay) * (cycle time).
As long as the effective delay is longer than the minimum requirement for the specific memory, then the unit should work in terms of latency and latching.
But note that faster clock signals might result in errors that might hinder working at said speed.
Example:
1. Memory run at DDR3-1333
Memory Clock= 166MHz
Cycle Time = 6ns
@ CAS 7, effective delay = 7 * 6 = 42ns (we can take this as a minimum required delay)
2. Same memory at DDR3-1066
Memory Clock= 133MHz
Cycle Time = 7.5ns
@ CAS 6, effective delay = 6 * 7.5 = 45ns (should work being longer than known minimum of 42ns above)
3. Same memory at DDR3-1600
Memory Clock= 200MHz
Cycle Time = 5ns
@ CAS 8, effective delay = 8 * 5 = 40ns (might work if the required latency of 42ns at DDR3-1333 is not the absolute minimum)
@ CAS 9, effective delay = 9 * 5 = 45ns (should work as it is longer than the minimum effective value of 42ns)
A stick of CAS 9 at DDR3-2000 has an effective delay of 9*4=36ns
Same memory at DDR-1333 has an effective delay of: 52.5ns @ CAS 7; 45ns @ CAS 6; 37.5ns @ CAS 5; and 30ns @ CAS 4.
Thus it should work all the way down to CAS 5 at least.
Others who know better can please add or correct me if needed