If the timing is the same, why different speed rating?
timings are based on the number of needed clocks for each spec of the ram. Each of the 4 numbers refer to different characteristics of how the ram performs.
As to the clock speeds, it gives you how fast a clock the ram can support. So between the two numbers (clock speed and timings) you can work out the time it takes the ram to respond to a issued action.
with the same timings, it comes down to the clock speed of the ram. At 1333Mhz, 1 clock is 20% slower than 1600Mhz. ie: 1333Mhz is about 0.75ns per clock. At 1600Mhz, that is 0.625ns.
as DDR is double rate (so effecting hot to work out timings), a could of 9 works out to be 3.375ns (1333Mhz) vs 2.8125ns (1600Mhz) needed for the issued action to complete.
now, if that difference is enough for you to pay the extra for the faster ram, that is up to you. You also have to remember that the speed of the ram is only one part of the equation as the information has to be requested by the cpu, passed through a memory controller, then read from the ram, then passed all the way back to the cpu before it can work on it (so giving a overall system ram access time). at that point, the extra speed is questionable for light users. In a lot of cases, most improvements in the Athlon range (going back a way here) was due to having a better memory interface speed than intel. Now both have the memory controller on chip, the difference is a lot less. IIRC it went from a total time measured (in software/bentchmarks) from several 100ns to only a few 100. The increase in system responciveness was massive.
Dual channel ram was introduced (you could say again) to address the memory issue. It did not help access times (just like raid 0), but it did mean if you needed a lot of data (and that is generally all the time), you could get the data at once instead of waiting for a second read to occur.
I mention "again" before as before DDR and SD-RAM, going all the way back to 30pin ram, RAM was setup in banks to allow for the larger memory bandwidths.