DDR and QDR memory - limits of its bandwidth still SDR?

[MadRat]

Since the interface for DDR and QDR technology is still a single 64-bit path is it not limited to theoretical SDR limits?

If I understand right then DDR takes advantage of dead time for the 64-bit SDR pathway by making a second series of memory banks queued for action so that the thoroughput of data is always sustained. QDR takes this one step further by making four series of memory banks queued for action, right? If this is the case then isn't the bandwidth still limited by the initial 64-bit pathway?

 

[Peter]

No, you understand wrong DDR doubles the transmission rate of the data, pumping a 64-bit word every half clock cycle. QDR teams two banks of DDR RAM up to transmit data every quarter of a clock cycle, alternating from either bank.

The 64-bit-ness is the WIDTH of all that, while the data rate enhancements SDR-DDR-QDR all address the SEQUENCE.

 

[MadRat]

So if its not simple interleaving why isn't DDR memory much faster than SDR?

 

[imgod2u]

While the data is sent at twice the theoretical speed of SDR memory, the access request and the row and column access latencies are still the same. So that DDR signal is only being used during the transmitting of the cacheline which usually lasts 4 clocks. The rest of the time, the data request, row access, column access, etc. is still sent based on a 1 signal per clock fashion.

 

[Peter]

... and of course, with the large caches and advanced prefetching technologies used in today's processors, the speed of the RAM array doesn't matter much except for very specific types of applications.

 

[MadRat]

Let me get this right, then. Sounds like the signalling is actually done with hi, lo, and off states in order to send the on-off signals to a pair of waiting buffers. The overhead in time it takes to arrange the signalling penalizes it as well as the normal latency of SDRAM technology? If DDR|| is built on the same technology then it sounds like serial technology should the way to go as it improves.

 

[Peter]

No. Serial technology has an even longer initial latency.

 

[MadRat]

Yeh, but you stream whole chunks of serial data and pick out what you want from a buffer whereas you pick and choose with parallel technology, right? With buffer sizes increasing on a regular basis you may not need the quick but slow interface of DDR as CPU speeds scale.

 

[Howard]

Peter is my god.

 

[Peter]

Originally posted by: MadRat
Yeh, but you stream whole chunks of serial data and pick out what you want from a buffer whereas you pick and choose with parallel technology, right? With buffer sizes increasing on a regular basis you may not need the quick but slow interface of DDR as CPU speeds scale.

Ummm ... I guess you lack some basic understanding of how these things work. With parallel RAM, you also stream (you say "burst" here) a set of data at once. Typically, you match up the processor model's cache line size, so currently any x86 chipset pumps (8) 64-bit "quadwords" per access, which, with DDR, typically takes some 13 or 14 clock cycles (about ten for the initial access, and then 3.5 for the remaining 7).

Serial RDRAM, even with its ridiculously high clock rate, wouldn't get anywhere near DDR throughput, weren't they running eight parallel data lines too AND running two memory controllers in parallel on the more advanced chipsets.

Large buffer sizes is actually something that may not be desirable in certain situations. You always trade latency and throughput - sure, RDRAM technology provides really nice performance in throughput bound applications (like image processing or media streaming), but it SUCKS (I mean it!) in latency bound apps (those that do more random access, like databases or file servers).
QDR, combining the lower latency of SDRAM technology with a yet again doubled throughput, will be veeeery interesting, particularly because it simply uses existing DDR SDRAM silicon plus a neat trick that will be done in some tiny add-on logic on the DIMM.