DDR 133Mhz VS 266Mhz

[Athos]

What is the advantage to using 133 x 2 rather than simply clocking at 266Mhz?

It would seem that on the data bus that you are going 266Mhz Even if you are only running the clock line at 133. Since there are 64 lines for SDRAM (72 w.ECC) it would seem that the single line at 133 has very minimal effect on power and RF issues.

Why add the complexity of a PLL (I assume that what is used) to divide the clock in half rather than just go 266?

 

[Howard]

Lower yields.

 

[Howard]

BTW, welcome to Anandtech.

 

[Athos]

I dont mean to disregard your answer but that is more of a consequence than a reason.

What is the cause of lower yeilds? Why is 133x2 easier to do?

Thanks, and I glad to be here.

 

[AndyHui]

Clock skew.

With the large number of parallel lines, it becomes harder to ensure that signals arrive on time, every time, the faster it is.

 

[Evadman]

Originally posted by: AndyHui
Clock skew.

With the large number of parallel lines, it becomes harder to ensure that signals arrive on time, every time, the faster it is.

Also the farther the distance, the harder it is to do. Memory is a little too far away from the north bridge currently.