Crays and distributed computing?

[Diffusion]

I was just reading some stuff on a mailing list I am subscribed too about Cray supercomputers. One person who seemed to have quite a bit of knowledge stated that Cray processors are vector based, meaning that they can add matrices together in one processor cycle, instead of going through one by one with each processor cycle consumed by an integer/floating point calculation. How would this transfer to the various distributed computing programs? For stuff like RC5 where you are trying many keys could you write the client to take advantage of this? Has anyone done something like this for any of the projects currently running?

 

[BurntKooshie]

Yep, they do vector processing...aka, SIMD. The old school way of doing it was "single instruction, multiple data" via different processors. Now they can do it within a register (SWAR - simd within a register). Altivec is a wide enough implementation of SIMD to work for RC5, which is why it does so phenominally well per clock, and is on a processow with enough (architectural vs. rename) registers that it's able to do it.

 

[JHutch]

To add to what BK said, if you've every heard any of us use the term "bitslicing" that is basically what the Cray would be able to do with the RC5 key. It allows the processor to work on multiple keys at once, thereby increasing the keys/sec output immensely.

JHutch

 

[bot2600]

I know the current pentuim 4s were tried with bitslicing and could not handle it, will this change as the speed increases or are the just limited because of their lack of registers? How will the new AMD chips handle this? It would be nice to see some smokin chips come out.

Bot

 

[BurntKooshie]

Lack of registers.

Maybe x86-64 will be able to be RC5 bitsliced (16 GPRs in 64-bit mode), but I sincerely hope RC5-64 is over before the hammer family comes out (sometime next year). I also hope that no one tries rc5- ">64" because that'd be absurd.