My wild-ass guess is that it's due to tiny electrical fluctuations in the phase-lock loop, producing a tiny variation from the electrical signal in the FSB. The clocking numbers you're dealing with are so high, my guess it's simply part of the electrical variations inherent in high-speed semiconductor architectures. I used to know a lot more about this then I now do. If you OCed a 80386-33 to 37 MHz (which I'm sure some people did) you would probably not see any variations at all, because the ceiling was so much lower. But now, with 3.3 GHz CPUs OCing to 4.3 GHz, or the equivalent quads, my guess is you're bound to see slight variations. I know next to nothing, of course.
Are you finally finished with the Q9650?