CPU+TPU

[legolas_tk]

Hello everyone.

This will be highly technical. I like to see if it is possible to design integrated CPU+TPU, like CTPU,
CPU includes (wikipedia):

1. datapaths (such as ALUs and pipelines)
2. control unit: logic which controls the datapaths
3. Memory components such as register files, caches
4. Clock circuitry such as clock drivers, PLLs, clock distribution networks
5. Pad transceiver circuitry
6. Logic gate cell library which is used to implement the logic

TPU includes:

1. Unify buffer
2. Matrix Multiply unit
3. Accumulators - sharing wtih ALU

Frequency 2Ghz minimum, at least 32MB cache and L2/L3 cache with 1.5V max voltage
both communicate with a integrated bus

Any comments are appreciated.

 

[sdifox]

So, lik EyeQ or Kirin 970? Google's approach makes sense to me so I am wondering why you want to integrate tpu to cpu.

This is interesting

https://medium.com/@CPLu/should-we-all-embrace-systolic-array-df3830f193dc

 

[legolas_tk]

CPU includes (wikipedia):

1. datapaths (such as ALUs and pipelines) - ALU with Matrix Multiply unit
2. control unit: logic which controls the datapaths
3. Memory components such as register files, caches
4. Clock circuitry such as clock drivers, PLLs, clock distribution networks
5. Pad transceiver circuitry
6. Logic gate cell library which is used to implement the logic

Eliminating the TPU, just use CPU with some TPU elements for basic TPU processing and offload to any TPU. How about that?

 

[Batboy88]

Cache is clearly not that Important though. Been Plenty of examples with Half or Less and Performed just as good or better.

 

[legolas_tk]

Any other tips to make this happen?