- May 16, 2008
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Just noting progress, first it began with the early chips, clock speeds increasing rapidly (P4 race to 10 GHz
).
Enter the Nehalem, Sandy/Ivy bridge, Haswell.
Nehalem clocked great, Sandy even better. Ivy bridge has been relatively worse, certainly no better at clocks, and Haswell appears to be another significant drop.
At the current rate as the process is getting smaller we are loosing overclockability as heat is becoming an issue. There is little to no incentive to upgrade for owners of the previous 3 gens (Haswell, Ivy, Sandy are all so similar imo). Then the extreme high end is lagging a generation behind in IPC (ivy E coming soon).
If we can no longer rely on clock increases, and IPC seems pretty hard to increase dramatically maybe they will finally start going massively parallel (many cores?).
What are your guys thoughts?
Enter the Nehalem, Sandy/Ivy bridge, Haswell.
Nehalem clocked great, Sandy even better. Ivy bridge has been relatively worse, certainly no better at clocks, and Haswell appears to be another significant drop.
At the current rate as the process is getting smaller we are loosing overclockability as heat is becoming an issue. There is little to no incentive to upgrade for owners of the previous 3 gens (Haswell, Ivy, Sandy are all so similar imo). Then the extreme high end is lagging a generation behind in IPC (ivy E coming soon).
If we can no longer rely on clock increases, and IPC seems pretty hard to increase dramatically maybe they will finally start going massively parallel (many cores?).
What are your guys thoughts?