At too low a temperature any clocked CMOS chip (ie. a CPU) will run into clock races - which occurs when the logic speed has increased so much over the wire delay that the signals (which are logic delays) will outrun the clock (which is wire delayed) and your end up with the signals winning the race (which is bad). The PLL may have problems too - since it's an analog circuit designed to run within a thermal envelope, so clock jitter and skew may be worse than anticipated. Despite the fact that it's about -80C out of spec., it will probably work though - there's a fair amount of margin designed in to CPUs to avoid races. Beware of thermal expansion/contraction problems caused by sharp temperature gradients. If you are crazy enough to try this, try to keep the temperature changes gradual or you will risk bump-pad shearing on BGA and FC-PGA parts.