CPU Power Density Trend?

[njdevilsfan87]

Is there a chart somewhere that shows microprocessor power density trend over the years? I've sort of come to realize that TDP is almost a useless number for us overclockers. How our cooling performs doesn't really depend on whether the chip dissipates 120W, 150W, 250W, or even 400W. I think Gigabyte advertised 600W cooling capability on one of their GPU coolers, which is kind of useless because more metal = more heat capacity. What it really depends on what the max power density is. For example, a giant non-existent 1000mm^2 chip could probably comfortably dissipate 400W (assuming relatively uniform heat dissipation) through air cooling, whereas my 355mm^2 5960X will hit 100C if pulling that much power using Prime95 AVX2 using custom liquid cooling. The reason I ask is because max power density is not as simple as reported wattage divided by chip area, because local power densities are much different from the mean.

I'm trying to get an idea of what is realistic, because TDP of the chip or even actual reported wattage isn't useful. My CPU pulling 250W will run a good 20-30C hotter than my GPUs pulling that same amount. And go figure, GK110 is a much larger die than the 5960X so maximum power density on the GK110 die itself may actually be less than that of my 5960X.

 

[Idontcare]

You want a trend of localized maximum within-chip power density across different chip designs and suppliers?

Even if one were to task themselves with going about the process of collecting that data under uniform testing conditions (AMD would test differently from Nvidia from Intel from Samsung from Apple, and all would be different from how you would test as a laymen), what would such a "trend" communicate to you?

That the design teams at some companies traded off creating localized hotspots in exchange for reducing the area of a specific given circuit or three within the core?

Not too mention the fact that "local power densities" are not solely systematic (by design) by also vary from chip to chip because of within-wafer process non-uniformities.

The physical location and value of the maximum power density in your specific 5960X could be unique to literally just your specific 5960X. So what relevance would there be in taking such data from just your 5960X and throwing it on a chart to generate a trend? I just don't see where you go with such a data set or the trend created with it.

 

[ClockHound]

You want a trend of localized maximum within-chip power density across different chip designs and suppliers?

What about non-local maximum within-chip power density across different chip designs, would that have a more satisfying ending?

I'm guessing the OP wants to know how tricky dissipating 140W+ will be with increasing density, 32nm > 20nm > 14nm.

 

[njdevilsfan87]

Even if one were to task themselves with going about the process of collecting that data under uniform testing conditions (AMD would test differently from Nvidia from Intel from Samsung from Apple, and all would be different from how you would test as a laymen), what would such a "trend" communicate to you?

It would be a lot more informative than TDP. Because neither air or liquid are limited by that. They're limited by maximum power density (after spreading out through the chip itself and reaching the surface of the die or spreader - whatever is in contact with the heat sink). Water cooling maximum potential (from what I've read some time ago and could be dated now) is about twice that of air's based off power density.

We have shrank down to the point where even on water I can hit a dangerous temperature long before I hit any dangerous voltage. That is why I want to know.

I'm guessing the OP wants to know how tricky dissipating 140W+ will be with increasing density, 32nm > 20nm > 14nm.

Exactly this. I understand each manufacturer would measure it differently, but as long as the measured area is large enough (say 5x5mm) there should be a standard deviation where everyone falls into despite variances and defects in manufacturing. I guess it doesn't exist because up until now there wasn't much a need for it. I think there is a need for it now. We cram more transistors into a small space faster than we can reduce power consumption for that same area.

 

[Idontcare]

What about non-local maximum within-chip power density across different chip designs, would that have a more satisfying ending?

I'm guessing the OP wants to know how tricky dissipating 140W+ will be with increasing density, 32nm > 20nm > 14nm.

Ha ha!

The process node has zero impact on power density. The definition of power density is heat per unit area.

Determine the power dissipated, determine the area, compute the density.

A 14nm based 100mm^2 chip dissipating 100W will have the exact same thermal density (power density) as a 20nm based 100mm^2 chip dissipating 100W.

Comparing thermal densities across chips is pretty easy to do once you know the power dissipated and the die size.

But I don't think this is what the OP wants to do. Or maybe it is but he didn't realize it at the time of posting? Will have to wait and see the OP's response to know.

 

[njdevilsfan87]

A 14nm based 100mm^2 chip dissipating 100W will have the exact same thermal density (power density) as a 20nm based 100mm^2 chip dissipating 100W.

Comparing thermal densities across chips is pretty easy to do once you know
the power dissipated and the die size.

That's not what I am getting at. The 14nm chip dissipating 100W is going to be smaller than the 20nm one, and thus have a higher power density.

We cram more transistors into a small space faster than we can reduce power consumption for that same area.

 

[Phynaz]

See my post here
http://forums.anandtech.com/showpost.php?p=33151036&postcount=33

 

[Xpage]

That's not what I am getting at. The 14nm chip dissipating 100W is going to be smaller than the 20nm one, and thus have a higher power density.

You are assuming that the 100W is maintained when shrinking the size of the die from 20nm to 14nm.

IDC stated 100mm sq to a 100mm sq chip doesn't matter if it is 20nm or 14nm as the area is constant as is the wattage dissipated. Which is correct.

If that 100mm sq went down to 66mm sq and still had 100W of heat dissipated then the density increases.


OR

maybe you are referring to local hotspot power density increasing, as a subportion of the entire chip, say one particular 10mm sq chunk, instead of the overall chip. That may be the case (that power density increased locally but not globally). Then I would assume that dark silicon will be needed next to it or low heat generating/infrequently used transistors will be by that area.

 

[Enigmoid]

I expect the OP is talking about something like this.

The vast majority of the die is using little power while certain areas are giant hotspots.

There is,as Idontcare said, that power density is simply related to power/area.

However the power heavy spots do not obey this trend. Their thermal density will depend on (architecture aside) the characteristics of the node. How much the node shrinks the primary power using areas vs. how much less energy is required on the smaller node. That is likely to be one of the primary driving factors in temperature vs. clockspeed for a given cooling capacity.

The other thing to note is that the primary power using areas of the die have been shrinking as more and more relatively low power stuff gets integrated into the CPU die. A P4 is pretty much all CPU + Cache while Haswell includes a memory controller, igp, PCI-E, display, etc. all of which will use relatively little power (and are relatively large in comparison to the power they use) meaning that the primary power using areas are smaller in relation to the total die size. That means that a 100W, 90 nm, 100 mm^2 P4 would have a lower thermal density and temperature than a 100W, 14 nm, 100 mm^2 die shrunk P4 as an SOC (assuming that the die shrinks do NOT reduce power more than they reduce size and that the 90 nm -> 14 nm actually gives a 100 mm^2 chip which it will not).