CPU power consumption as a function of frequency and voltage

[DRavisher]

I've seen it stated on this forum and elsewhere, that the power consumption of a CPU is proportional to the simple forumla f*V^2, with f the frequency and V the voltage. Is this formula actually accurate, or is it a very crude forula only valid for small changes in frequency or voltage? For instance, AMD's Griffin mobile processor is supposed to be able to lower it's frequency to 1/8 of max (according to an anandtech article). Assuming that the voltage can be lowered by, say, 20% at the same time, this would give a power consumption of only 8% of max.

If this truly is accurate, then I must ask, why hasn't Intel allowed their mobile processors to clock lower? My 1.2 GHz Core 2 Duo (ULV) only goes down to 800 MHz, while a 2 GHz Griffin would be able to go down to 250 MHz. Is there some technical challenge in lowering the multiplier this low, or isn't the power savings potential as large as the simple formula above would indicate (and therefore Intel simply hasn't bothered doing it)?

 

[BrownTown]

In terms of power consumption there are several forms and causes that you cannot model them all in one simple formula. However a very good approximation is to assume that there are two forms of power consumption, dynamic and static. The static power consumption is equal to some constant times voltage squared ( k1*V^2 ), dynamic is equal to another constant (usually jsut assumed to be the capacitance) times the frequency times the voltage squared (k2*f*V^2). The constants are factors of the size of the chip and the process used. In a modern process the static power consumption can be as big as the dynamic power consumption, so your formula is not entirely valid since lowering the frequency will not affect the static power loss at all. In terms of lowering power loss the best way given a certain chip is to lower the voltage, this has a HUGE effect on power consumption. Lowering the frequency is also very good, but only to a limit.

Also of note is that different processors also have so called "sleep states" where whole areas of the chip are powered down, so if you are in a lower level sleep state you are actually reducing not just the frequency and voltage but also the capacitance. As for clocking the processor so low, you have to remember that there are tons of other things inside a laptop burning power other than just the CPU. If your sleep state gets you from 30W down to 5W then that is usually gonna be good enough and going even further to 2W really doesn't gain you much.

 

[Onund]

Originally posted by: DRavisher
I've seen it stated on this forum and elsewhere, that the power consumption of a CPU is proportional to the simple forumla f*V^2, with f the frequency and V the voltage. Is this formula actually accurate, or is it a very crude forula only valid for small changes in frequency or voltage? For instance, AMD's Griffin mobile processor is supposed to be able to lower it's frequency to 1/8 of max (according to an anandtech article). Assuming that the voltage can be lowered by, say, 20% at the same time, this would give a power consumption of only 8% of max.

If this truly is accurate, then I must ask, why hasn't Intel allowed their mobile processors to clock lower? My 1.2 GHz Core 2 Duo (ULV) only goes down to 800 MHz, while a 2 GHz Griffin would be able to go down to 250 MHz. Is there some technical challenge in lowering the multiplier this low, or isn't the power savings potential as large as the simple formula above would indicate (and therefore Intel simply hasn't bothered doing it)?

In terms of pure digital circuits: P = f*c*V^2
Where c is the capacitance.

So proportional yes. Actually what you need is a change in state, from high to low or low to high. The difficulty comes from not when a change of state will occur and the actual capacitance.

Say you have a simple inverter that's being fed a constant clock. This would be fairly easy to calculate because you know there's a change in state every clock pulse. You also can calculate the capacitance fairly accurately.

When you scale this up and include combinational logic and memories, it gets very hard to know what's going on exaclty. Here you talk in terms of probability of changes and equivalent caps... In general though, if the frequency lowers of the voltage lowers you get an idea of how much power savings you'll get.

Another thing to consider when talking about complex circuits (meaning more than just an NAND gate or decoder...) is you'll have lots of analog circuits in there too. PLLs, regulators, reference blocks, stuff that burns current. At some point the analog power consumption would become dominant I would guess.

As for Intel not allowing a slower clock, it may have to do with the PLLs. I really don't know the interal structure of the CPUs but if there are multiple PLLs in there they may be limited by what downstream PLLs can accept as the lowest input clock.

 

[Special K]

Originally posted by: BrownTown
so if you are in a lower level sleep state you are actually reducing not just the frequency and voltage but also the capacitance.

Why would you say that entering a sleep state would decrease the capacitance? Exactly which component of capacitance are you referring to?

 

[BrownTown]

Originally posted by: Special K

Originally posted by: BrownTown
so if you are in a lower level sleep state you are actually reducing not just the frequency and voltage but also the capacitance.

Why would you say that entering a sleep state would decrease the capacitance? Exactly which component of capacitance are you referring to?

You are reducing the surface area of the "capacitor" since you are powering down certain sections of the chip. For example I know the L2 cache is powered down at some point, and when you do that you are reducing the capacitance and the power and clock nets as well as whatever logic is interfacing with the cache.

 

[Special K]

Originally posted by: BrownTown

Originally posted by: Special K

Originally posted by: BrownTown
so if you are in a lower level sleep state you are actually reducing not just the frequency and voltage but also the capacitance.

Why would you say that entering a sleep state would decrease the capacitance? Exactly which component of capacitance are you referring to?

You are reducing the surface area of the "capacitor" since you are powering down certain sections of the chip. For example I know the L2 cache is powered down at some point, and when you do that you are reducing the capacitance and the power and clock nets as well as whatever logic is interfacing with the cache.

How exactly are you implementing the sleep mode? The most common implementation is to place a large PMOS device (or many smaller ones in parallel, which would be a more realistic scenario) between VDD and the pull up network, and a large NMOS device between ground and the pull down network. During normal operation, both of these devices are turned on to provide VDD and GND voltages to the circuit.

When sleep mode is entered, these devices are shut off, and the circuit sees a "virtual VDD" and "virtual GND". These nodes are floating, but will typically settle to a very low voltage, which reduces leakage. The switching factor alpha would also be reduced, since presumably none of the signals, including the clock, would be toggling in a logic block that was in a sleep state. I don't see how it would reduce the capacitance, however.

 

[CTho9305]

I don't see how it would reduce the capacitance, however.

There's two ways of looking at it:
1) reducing the switching capacitance, and not using an alpha
2) reducing the alpha, and considering the total capacitance

When you're saying "alpha would also be reduced", that's the same as saying, "the actual cap that's switching is reduced".

 

[TuxDave]

Originally posted by: Special K


How exactly are you implementing the sleep mode? The most common implementation is to place a large PMOS device (or many smaller ones in parallel, which would be a more realistic scenario) between VDD and the pull up network, and a large NMOS device between ground and the pull down network. During normal operation, both of these devices are turned on to provide VDD and GND voltages to the circuit.

When sleep mode is entered, these devices are shut off, and the circuit sees a "virtual VDD" and "virtual GND". These nodes are floating, but will typically settle to a very low voltage, which reduces leakage. The switching factor alpha would also be reduced, since presumably none of the signals, including the clock, would be toggling in a logic block that was in a sleep state. I don't see how it would reduce the capacitance, however.

You're pretty much right. The big win in sleep states where you collapse the power rails is the fact that you can eliminate a large source of leakage power. I think the reduction of capacitance needs to be changed to the reduction of "active capacitance" where that equals the average activity factor * static capacitance (excluding the details of Miller feedback).

Besides that, the equation that you had in your OP is a simple equation for active power and ignores the component of leakage power.

Here's some fake numbers to give an example:
100W under max load is magically broken down into

Global control blocks running at slower clock frequencies which never power down
a) 10W of active power
b) 10W of leakage power

Digital logic blocks running at fast clock frequencies which can power down
c) 40W of active power
d) 40W of leakage power

So we can say Idle = a+b+c and Max = a+b+c+d

Dropping the frequency will mostly reduce c.
Introducing sleep states will mostly reduce d.