I assume by PCB you started off with a wire wrap design? Unless you plan on building more than a couple of them a wire wrap board with 74HC chips on it should be fine for testing a cable. If you have more than 50 gates, you probably are past the point of a wire-wrap board.
I work more on the FPGA side of things, but I believe the information I am providing should be accurate for the CPLD side.
Verilog is pretty easy to learn and there are many tutorials online. VHDL was designed by the military and is pretty messy IMO and more complicated than it needs to be, but there are some things that can be done in VHDL that become quite difficult with Verilog. Both are popular. I assume you have some knowledge of logic design to come up with the gate logic.
If you already have the logic using gates, you don't necessarily need to learn either of the above. Xilinx's Foundation (older) and ISE (newer) both allow you to build a schematic with the gates. Verilog and VHDL are much easier to work with on a large project, but if you want to stick with gates you can.
So you have XC9572-?PC44C? The ? is going to be either 7, 10, or 15 and is the speed rating. The XC9572 has about 1600 usable gates.
If you are testing 40 pins with a 44 pin chip (probably about 30 of which will be usable) you probably will need at least 2 CPLDs on the board to test all the pins. You will still need to put the CPLDs onto a board.
You can start off my downloading
Xilinx ISE Webpack (a crippled version) and seeing if that is what you are looking for. The Coolrunner II design kit for $50 that was mentioned uses an XC2C256-7TQ144. Xilinx's main Web page and support site (free membership) has a ton of information that can get you started. If you have a Xilinx sales rep, I am sure they would be happy to point you in the right direction.