CPI of pipelined processor

[gstekboy]

a non pipelined processor runs at 1.2ghz and has CPI 3 cycles.
Another processor with same instruction set has a 5 stage pipeline ,Find the increase in throughput at the same frequency ,given stalls occurs at 30% of instruction executed?

help me to solve this.

 

[ThatsABigOne]

Want us to do Computer Organization homework for you? Have you asked your TA's or professor? Show how you attempted this problem first.

 

[gstekboy]

Want us to do Computer Organization homework for you? Have you asked your TA's or professor? Show how you attempted this problem first.

for unpipelined

cpi = 3 cycle
clock cycle = .83ns


for pipeline

cpi = 1+ pipeline stall
= 1.3


throughput = 3/1.3 =2.3.

is the above answer correct

 

[Cerb]

Who knows? Not enough information was given. 30% of instructions stall, but for how long? It doesn't say 30% of cycles are stalled. Also, are the instructions stalling on both? If they are stalling on both for the same amount of time, then I guess the throughput difference could be figured anyway, but that's just one more assumption.

But, your CPI measure for the pipelined processor is (a) different than the non-pipelined processor (why isn't it the same?), and (b) if the difference to figure out is throughput, CPI is not the right measure, except to find the upper limit in IPC of the non-pipelined processor.

 

[Ken g6]

Hm, I can come up with at least two plausible scenarios. It could be that the instructions that stall the pipeline do so because they're complex, in which case they stall for at most 3 cycles.

Or the instructions that stall the pipeline could be branches, in which case they could stall the pipeline until the branch is resolved. Lacking information on where in the pipeline the branches are resolved (for most modern processors it's as early as possible), I'd have to assume it takes all 5 stages. I'd also have to assume that each pipeline stage takes only 1 cycle.

In this case I'd say I think you're close to the right answer, but not by the right method.

Edit: I forgot to divide. Not close at all.

 

[sushiwarrior]

If the stalls require a pipeline flush, then you have 30% of all instructions requiring an additional 5 cycles. This means you have (1.2GHz * 0.7) + (1.2GHz/5 * 0.3) (this is similar to saying: 70% of the time, 1 instruction is completed per cycle at 1.2GHz, 30% of the time the instruction takes 5 cycles to complete) if my quick mental guess is somewhat close. If they simply require a stall/halt (1 cycle? Maybe more? Question is not clear enough) then the question is kind of hard to answer without more info.