Could AMD use mismatched CCX?

[PeterScott]

I don't really expect to see it in PCs (except maybe in mobile targeted SoCs, like Intel's supposed Lakefield chip). But I was wondering whether we might see it in the next generation consoles.

And having to briefly change process is still a big cost, even for a nice big CPU. All the branch prediction and execution units in the world won't help when you need to flush the pipeline and dump branch predictor state because you switched process. There's a reason why Game Mode can help with minimum framerates.

It's not about context switching it's about overall load. Context switching is unavoidable. Games don't have 4 threads that can get exclusive use of 4 cores, Games have ~40 threads, constantly switching in and out.

Game mode is garbage. Does nothing for high end PCs, and only helps on low end PCs if you are dumb enough to trying running other applications while gaming on it. It really isn't about minor OS background processes.

What it really does is help in situations were you are essentially at 100% CPU utilization while attempting to game an stream video at the same time (or whatever other application your run while gaming). What it does is starve those applications of CPU.

In these kinds of fully loaded situations, losing a big powerful core to replace with smaller cores, makes things worse, not better.

Load matters much more than context switches today.

 

[amd6502]

I could see puma or an fdsoi excavator having area or power savings advantages over zen when very little performance is needed. However, like somebody said on page 1 of this thread, it's not worth the software support bother at this time.

If it is at some point, puma would be a candidate since it's easier to port to 12/14nm while excavator would make little sense. And I think it'd only make sense in very lower power APUs. Like a small APU with a single 1c/2t Zen core plus 4c/4t puma. The puma quad could have a large L2 (~4MB) that would also serve as the L3 for the zen core. In low power mode all but 2c/2t of puma would be powered down and it would take almost no power to run.

A simpler way to achieve big.little capabilities without composite heterogenous CPUs would be to have a multithreading non-SMT mode for Zen. A mode that a zen core or CCX could have that would make SMT non-symmetric. When entering this mode you would have one priority thread and one background thread per core. This arrangement would have some nice benefits and some IPC advantages for a wide range of CPUs, from 2c/4t APUs all the way to 16c/32t AM4 products and even threadrippers.