Component stress & timings

[nevbie]

I've read that higher clock speeds and higher voltages result in more component stress.
Now, there aren't any configurable timings for CPU (or i don't know about those), but there are for RAM at least.

Will tighter timings stress RAM more than loose timings?
Or perhaps timings and clock speed are similar things in practise and the answer would be yes?

And i mean (physical) "stress" that causes components to fail, not just some errors/instability.

 

[tcsenter]

Originally posted by: nevbie
And i mean (physical) "stress" that causes components to fail, not just some errors/instability.

Any time current is moving through a circuit, there will be some form of "stress" placed on something to some degree or another. Is that specific enough for you?

Within any frequency/voltage/loading envelope, configurable timing parameters are not going to fundamentally influence component failure. The failure is going to happen, maybe a little sooner or later depending on timings, but its going to happen.

Frequency, voltage, and loading can influence component failure if they are at the boundary or in excess of safe limits.

 

[nevbie]

Originally posted by: tcsenter
The failure is going to happen, maybe a little sooner or later depending on timings

The "maybe" here, it's my question.

Perhaps a bit too technical/unimportant to be asked though.

Any time current is moving though.. does a higher frequency increase that time? or just cut it in smaller pieces?

I guess lower timings would allow more requests to be fulfilled by the RAM then, hence more work and more stress (when the time period stays the same). Sounds just like frequency..?

 

[tcsenter]

Originally posted by: nevbie

Originally posted by: tcsenter
The failure is going to happen, maybe a little sooner or later depending on timings

The "maybe" here, it's my question.

Well again, the failure is probably inevitable due to an existing defect somewhere. More aggressive timings are not going to cause failure where some weakness or frailty didn't exist already. But yes, more aggressive timings will stress the entire memory subsystem more than relaxed timings, from the memory controller to the DRAM IC.

On Edit:

That said, if we are talking about memory that is already overclocked and overvolted, then aggressive timings can be the added/compounding stressor that pushes something to the point of imminent failure, as opposed to non-imminent though still inevitable failure.