Clockless chips: How long will it be till mainstream desktop procs are clockless?

[zsouthboy]

Yes....i know the P4 has clockless elements already already, and I know that clockless chips are a major pain in the arse to design and produce.....but when? and what major obstacles still lie in the way?

And.....how do you go about marketing a clockless chip?

zs

 

[SuperTool]

First of all, a clockless processor is not a machine, it's a living thing Everything just flows through it at its own pace. One of the most beautiful things in CPU design.
Major obstacles to clockless:
1. Virtually untestable. It would be very difficult to write tools because you cannot freeze state by turning off the clock, and no scan chains. You have to carefully test each circuit as a whole, so hard to make big circuits. That's why it's mainly used for memories and etc.
2. No tools, therefore noone is designing asynch. Noone designing async- therefore no tools.
3. Dual rail. Each signal needs 2 wires for handshaking. If you think routing is a pain in the butt now, with async you have to double it.
4. I took an async course. We had to write gate level async CPU. Hated every second of it. No engineer in his right mind is going to sit there and write handshaking expansions till the cows come home. Instead of logic, this is discreet math. RTL is so much easier.
5. Not much demand so far. People want MHZ.

If I had to venture to say, I think it's going to be another 10-20 years before we see fully asyncronous CPUs mass produced commercially outside of research centers. There is a lot of research going on, but also many obstacles.

 

[zsouthboy]

Hmmmm....maybe someone will discover some totally outrageous thing that fixes every one of those probs.....but.....I doubt it

Even though people want mhz, I think notebook people would like the extra battery life, so would handheld users

Hehe.......you know what'll be really funny? When they do come out and you run like Sandra 2020 or whatever and get a a weird cpu result......of course I'm sure by then we'll be flying around in rocket cars, etc.

zs

 

[MustPost]

I read in an MIT journal that Intel made a clockless version of the Pentium, not mass produced of course. And they may have made a clockless version more recent procs as well, but I think they have seriosly scaled back on clockless chip R&D since.

 

[CSoup]

SuperTool,

Did you take Rajit's class? I only attended a few lectures, but really wanted to take it, but he stopped offering it. Now he puts a little of the Async stuff in the new VLSI course. People really hate this new course because he rushes through the synch stuff so that he can teach some asynch. Not a good idea. Also, like you say, EE's don't like to do that handshake expansion stuff. Asynch is more for the CS guys.

 

[SuperTool]

<< SuperTool,

Did you take Rajit's class? I only attended a few lectures, but really wanted to take it, but he stopped offering it. Now he puts a little of the Async stuff in the new VLSI course. People really hate this new course because he rushes through the synch stuff so that he can teach some asynch. Not a good idea. Also, like you say, EE's don't like to do that handshake expansion stuff. Asynch is more for the CS guys. >>



Yeah, I took Rajit's class. EE571. He is Asynch Guru and Crusader. I don't think he likes sync that much Really brilliant guy.
And man was it confusing. Too bad I graduated. Looks like some cool classes being offered now. Maybe I should come back for a masters I don't know if I can take any more Ithaca though

 

[mrUnderdog]

go MIT!

sorry

 

[TheOmegaCode]

I've never posted in the Highly Technical forum, and I probably wont for a while again.... But it is to my understanding that clockless chips are only functional when all components are intertwined, thereby eliminating any need for a bus or a clock rate. Everything functions together... I may be wrong...

 

[Xalista]

Supertool wrote:


<<
First of all, a clockless processor is not a machine, it's a living thing Everything just flows through it at its own pace. One of the most beautiful things in CPU design.
Major obstacles to clockless:
1. Virtually untestable. It would be very difficult to write tools because you cannot freeze state by turning off the clock, and no scan chains. You have to carefully test each circuit as a whole, so hard to make big circuits. That's why it's mainly used for memories and etc.
2. No tools, therefore noone is designing asynch. Noone designing async- therefore no tools.
3. Dual rail. Each signal needs 2 wires for handshaking. If you think routing is a pain in the butt now, with async you have to double it.
4. I took an async course. We had to write gate level async CPU. Hated every second of it. No engineer in his right mind is going to sit there and write handshaking expansions till the cows come home. Instead of logic, this is discreet math. RTL is so much easier.
5. Not much demand so far. People want MHZ.

If I had to venture to say, I think it's going to be another 10-20 years before we see fully asyncronous CPUs mass produced commercially outside of research centers. There is a lot of research going on, but also many obstacles.
>>



First, your remark. I agree, the principle of async circuits is beautifull.

Now, for your major obstacles.

1 Yes, it is a lot more difficult to test an asynchronous circuit, but it is by no means impossible. Philips is a few years ahead off everyone else in async circuits (they have some async designs that are selling by the millions). I know for a fact that Philips has tools that add the circuitry needed to make an async design testable. I also know that right now this added circuitry is still more than what is needed too make a sync design testable.

2 Philips has tools (called Tangram), I have worked with them myself on a project in a VLSI course I took. Our proffesor was the leader (and starter) of the async circuit project at philips. You might say that he is (one of) the father(s) of asynchronous circuitry. The tool is quit mature now and C. van Berkel (the professor) is only involved in the testing part off the tools right now. I am graduating a Philips Natlab in the Netherlands right now and one off my fellow graduate students is working with Tangram to design yet another embedded processor with it.

3 Dual rail is not an issue anymore. One of philips employees that works in the group that I am in right now develloped single rail technology for his Ph.d. thesis. But I think you are talking about dual track, which is like dual rail, only in the control part of the design (so dual rail is data path). Yes, the control part still uses dual track, but Philips has develloped single track technology also, but this turned out not to have many pro's.

4 I loved every second off my async VLSI course, but I can imagine that it sucks if you don't have access to tools. On the other hand, I imagine that this holds for sync. too. Handshake expansions aren't that bad.

5 Not in embedded. Power is a mayor issue there too.

I agree with you that it is going to take a long time untill we will see async. CPU's in our PC. I know philips has no immidiate plans to make (very) highspeed designs (Tangram wasn't designed for that, it was designed for low power.) However, you can buy async embeded designs like an async. 8051 TODAY!