ClawHammer in October?

[AGodspeed]

http://www.amdzone.com/#6

I've received some information from an anonymous source about the Hammer and Thoroughbred that could have possibly originated from Cebit. This information is not verifiable as AMD does not comment on unreleased products, but there are some very interesting details:

- Thoroughbred-initial release at 1800+ to 2200+
- Barton-released only if demand is there.
- SOI-gain in MHz of 10-15%
- Athlon-demand dictates product life
- Clawhammer-release and availability in October
- Hammer chipsets-AMD will be sole manufacturer for some time after release
- Clawhammer pricing-similar to Athlon pricing
- Athlon/Duron SMP-non MP versions SMP capability to be removed
- Hammer performance-P4 has no chance to come close in 32bit

 

[spanky]

i just hope mobo prices will be reasonable.

 

[goog40]

<< - Hammer performance-P4 has no chance to come close in 32bit[/i] >>



teehee

Will they be able to produce enough mobos to meet the initial demand?

 

[mchammer187]

i'll believe it when i see it

but it would be very nice if it were true

 

[Anand Lal Shimpi]

<< SOI-gain in MHz of 10-15% >>



I'm very skeptical of this. Remember that AMD's 0.13-micron SOI process still only uses partially-depleted SOI transistors which, as far as my understanding goes, does not offer much of a gain in terms of reduction in leakage current vs. non-SOI transistors. A 10 - 15% clock speed gain is claiming a bit much IMHO.



<< Barton-released only if demand is there >>



I personally see no reason for Barton. Even if the Athlon XP falls behind a bit, as long as AMD is within 10% in the performance numbers I see no need to devote time to getting SOI ready for mass-market ahead of schedule. Hammer should be the top priority.



<< Hammer performance-P4 has no chance to come close in 32bit >>



Provided that the Hammer performs no slower than the Athlon XP in the worst case scenario (I see no reason why it should) then this is quite possible. Remember that Prescott still a H2-2003 part and after the P4 gets the 533MHz FSB there won't be any other improvements outside of clock speed until Prescott (AFAIK).



<< Hammer chipsets-AMD will be sole manufacturer for some time after release >>



This would not be a good thing. VIA has already been working on a Hammer chipset for a while, I would be surprised if AMD were the sole provider of chipsets for this processor. They don't want the Hammer to launch to mimic the Athlon launch in '99 by any means.

Just my $0.02.

Take care,
Anand

 

[Wolfsraider]

******CONFIRMED******


thanks anand

 

[NFS4]

<< << Hammer chipsets-AMD will be sole manufacturer for some time after release >>



This would not be a good thing. VIA has already been working on a Hammer chipset for a while, I would be surprised if AMD were the sole provider of chipsets for this processor. They don't want the Hammer to launch to mimic the Athlon launch in '99 by any means. >>


I would have to agree with Anand on this one. According to this PR, everybody and their grandma is going to be ready at Hammer launch:

AMD announces chip set and third-party support for 'Hammer' 64-bit processor line

 

[jeffrey]

<< ClawHammer in October? >>


Your thoughts on this one Anand?

 

[AGodspeed]

I'm very skeptical of this. Remember that AMD's 0.13-micron SOI process still only uses partially-depleted SOI transistors which, as far as my understanding goes, does not offer much of a gain in terms of reduction in leakage current vs. non-SOI transistors. A 10 - 15% clock speed gain is claiming a bit much IMHO.

This brings up a good question. Are there any substantial benefits of SOI for the Athlon or Hammer processors given the price premium of SOI?

Will they be able to produce enough mobos to meet the initial demand?

Remember that AMD has a deal with UMC goog40. UMC can produce as much as 20% of AMD's total processor output (that 20% figure comes from a contract with Intel a while back). Knowing that AMD shipped approx. 31 million processors last year, UMC would be able to produce over 6 million AMD processors (AMD has said UMC will produce only .13-micron K7 processors) and that would mean AMD would have a lot more room to ramp up ClawHammer (and eventually SledgeHammer) supply.

AMD plans on shipping more than 31 million processors this year (not taking UMC's contribution into account) because Fab 30 in Dresden still has a lot of room to grow (at capacity, Fab 30 will supposedly be capable of 50 million processors per year, which is scheduled for the end of 2003).

Although AMD will be able to produce more than 31 million this year when you look at how many more K7's you get once the .13-micron conversion takes effect.

 

[BD231]

Hammer chipsets-AMD will be sole manufacturer for some time after release

Hopefully AMD wont get in a hissy about "everybody and their grandma" trying to make ends on their new processor. It dosn't seem like AMD is really in much of a position to do such a thing, but I cant help but think that some legal propaganda may pop up.

 

[kuk]

Then again, what will the Hammer chipset be made of? ... the great part is the memory controller, which will be built into the processor die. Then there will be the AGP bridge, which would be a simple chip. And finally, a south bridge conected through HT, that could even be an nForce MCP. This south bridge could even host the AGP bridge.

I dunno what will be considered chipset from now on in the Hammer family ... but Of course, that's just my opinion; I could be wrong.

Edit: When introduced, the AMD-8000 series of chipsets will include the AMD-8111? HyperTransport I/O hub, the AMD-8131? HyperTransport PCI-X tunnel, and the AMD-8151? HyperTransport AGP3.0 graphics tunnel.. Then again, it's quite understandable why there's not much to develop on top of this.

 

[NFS4]

<< Then again, what will the Hammer chipset be made of? ... the great part is the memory controller, which will be built into the processor die. Then there will be the AGP bridge, which would be a simple chip. And finally, a south bridge conected through HT, that could even be an nForce MCP. This south bridge could even host the AGP bridge.

I dunno what will be considered chipset from now on in the Hammer family ... but Of course, that's just my opinion; I could be wrong. >>


Hey, lay off my sig foo

 

[Anand Lal Shimpi]

<< ClawHammer in October? >>


It's too difficult to say at this point. If the CPU is ready I can definitely see AMD giving OEMs and System Integrators chips by October but leaving the official launch until one month later to coincide with Comdex (more publicity).


<< This brings up a good question. Are there any substantial benefits of SOI for the Athlon or Hammer processors given the price premium of SOI? >>


What most people don't understand is that there is more than just SOI vs. non-SOI transisters. From the reading I've done it seems like the improvements of partially-depleted SOI transistors over non-SOI are marginal in comparison to the move to fully-depleted SOI. Ask an analog engineer and he'll give you information about the vast decrease in leakage current when moving to FD-SOI but as far as what sort of clock speed improvements (more appropriately, lower voltages) can be achieved, it's very difficult to say without knowing a lot more about Hammer.

pm, have any input on this (since I know it's right up your ally )?


<< Hopefully AMD wont get in a hissy about "everybody and their grandma" trying to make ends on their new processor. >>


I don't see this happening at all. AMD isn't in the chipset business, they make processors and anything they can do to sell more processors they will do. I don't see AMD limiting chipset supply at all.


<< Then again, what will the Hammer chipset be made of? >>


At the bare minimum you have the AGP bridge and the equivalent of a South Bridge. Integrated video is where the money is and thus you'll see the AGP bridge become something with an integrated GPU (Radeon IGP, nForce IGP, etc...). What will be interesting is to see how chipset manufacturers tackle the issue of memory for these integrated GPUs? Using the CPU's embedded memory controller is one approach but embedded DRAM also comes to mind here.

Take care,
Anand

 

[NFS4]

<< Hopefully AMD wont get in a hissy about "everybody and their grandma" trying to make ends on their new processor. >>


Why would AMD get mad about SiS, VIA, ALi, and NVIDIA making chipsets for their new chip?? Heck, AMD LOVES that That frees up production room for them. AMD has done this since the original launch of the Athlon. AMD makes the reference platform, then lures the rest of the chipset makers in to take the burden off their shoulders. With the original launch of the Athlon, there was the AMD750 chipset. Once the KX133 started to take over, AMD stopped production. AMD relied soley on VIA with the launch of the socketed versions of the Thunderbird with the KT133. While there were AMD750 based socket boards around, they were few and far between. With the Thunderbird + DDR, AMD's 760 chipset was the platform to bring DDR to the forefront. But once the KT266A , nForce, and ALi Magik 1 started making inroads, AMD bailed on the 760 chipset (the only reason why AMD760 stayed around for so long is b/c KT266 was a$$-like in performance).

The same thing will most likely occur with the Hammer. I have the feeling that AMD backed boards will show up at first in more #'s and for a pretty hefty premium. A month or two after launch, you will start seeing VIA, SiS, and NVIDIA solutions (most likely integrated solutions with SiS and NVIDIA). I don't know about ALi, they still seem kinda sketchy to me.


<< At the bare minimum you have the AGP bridge and the equivalent of a South Bridge. Integrated video is where the money is and thus you'll see the AGP bridge become something with an integrated GPU (Radeon IGP, nForce IGP, etc...). What will be interesting is to see how chipset manufacturers tackle the issue of memory for these integrated GPUs? Using the CPU's embedded memory controller is one approach but embedded DRAM also comes to mind here. >>


Aren't we talking $$$$$$$$$$ when we start mentioning embedded DRAM??:Q

 

[pm]

<< << This brings up a good question. Are there any substantial benefits of SOI for the Athlon or Hammer processors given the price premium of SOI? >> >>



Power drops due to reduced substrate leakage. Switching performance improves by approximately 10-20% on 0.13um (depending on the level of optimization that you perform on circuitry). Packing density (transistors per given area) improves by approximately 10-20% (depending on how hard you push the process rules) due to improves that can be made in well spacings and other key process spacings due to the reduced worries about latch-up on PD SOI.



<< What most people don't understand is that there is more than just SOI vs. non-SOI transisters. From the reading I've done it seems like the improvements of partially-depleted SOI transistors over non-SOI are marginal in comparison to the move to fully-depleted SOI. Ask an analog engineer and he'll give you information about the vast decrease in leakage current when moving to FD-SOI but as far as what sort of clock speed improvements (more appropriately, lower voltages) can be achieved, it's very difficult to say without knowing a lot more about Hammer.

pm, have any input on this (since I know it's right up your ally )? >>


Nice to see you posting, Anand. FD (Fully Depleted) is definitely better from an electrical standpoint than PD (Partially Depleted). One way for people to think about it is that there are three sources of leakage on conventional CMOS processes: substrate, Ioff, and gate. PD SOI solves the first one. FD solves the first and the second. A high-K dielectric can mitigate the third. Aside from the increased contact resistance, there's not much of a downside to FD SOI from an electrical standpoint. But from a cost standpoint a lot of people are trying to figure out how FD SOI wafers can be manufactured to the tolerances required on a 12" wafer. The task is far from trivial and will require a lot of time to figure out. PD is about the best anyone can hope for right now.

As far as the original question, I have no idea what Hammer clockspeeds will be and would not like to speculate. Most academic papers on SOI quote an approximate 10-20% transistor switching performance improvement on SOI over bulk on 0.13um. The range is based on how far you optimize the circuitry for SOI - some idealized SOI structures require completely different types of circuits to make best use of SOI and this makes porting of current designs over more difficult. Also there is a range due to the way that designers deal with SOI effects such as the hysteresis effect. There are various approaches to these problems that result in varying levels of optimization.

Patrick Mahoney
Microprocessor Design Engineer
Intel Corp.

 

[kuk]

<< Integrated video is where the money is and thus you'll see the AGP bridge become something with an integrated GPU (Radeon IGP, nForce IGP, etc...). >>



But considering the fact that these CPUs will be offered as a high-end solution in the beggining, it makes sense that AMD will want to be the only chipset supplier for a while. Until Clawhammer goes completely mainstream (momma, pop and sis buying one ), there's little sense on going integrated GPU. Of course, maketing could hype-up anything they want, but I don't see a market for different chipsets for the Hammer family at launch.



<< What will be interesting is to see how chipset manufacturers tackle the issue of memory for these integrated GPUs? Using the CPU's embedded memory controller is one approach >>


Wouldn't there be latency issues from going GPU -> CPU (Memory controller) -> Memory, and then back again? Of course, no one would make a mobo were one dimm slot would be reserved for video memory, with direct access to the GPU. OK, i'm going kuku here.)



<< but embedded DRAM also comes to mind here. >>


Can we say ... BitBoys Oy?

 

[Anand Lal Shimpi]

<< The same thing will most likely occur with the Hammer. I have the feeling that AMD backed boards will show up at first in more #'s and for a pretty hefty premium. A month or two after launch, you will start seeing VIA, SiS, and NVIDIA solutions (most likely integrated solutions with SiS and NVIDIA). I don't know about ALi, they still seem kinda sketchy to me. >>


Hopefully that's not the case. I'd like to see solutions from at least one other manufacturer at the launch of the processor. If done right, Hammer could easily become a pretty hard hitter before '02 is over with.


<< Aren't we talking $$$$$$$$$$ when we start mentioning embedded DRAM?? >>


Possibly, it depends on a number of factors but it's something that could happen in the future. Remember we're not talking about huge amounts of memory here, and the die size taken up will drop as the chips move to smaller manufacturing processes. It's an idea, definitely not something that'll be used anytime soon.


<< Nice to see you posting, Anand. FD (Fully Depleted) is definitely better from an electrical standpoint than PD (Partially Depleted). One way for people to think about it is that there are three sources of leakage on conventional CMOS processes: substrate, Ioff, and gate. PD SOI solves the first one. FD solves the first and the second. >>


Good to see you too pm. The Ioff leakage is what I was thinking of when mentioning the benefits of FD-SOI over PD-SOI. Thanks for the input on SOI, it looks like it could account for a decent clock speed improvement.


<< But considering the fact that these CPUs will be offered as a high-end solution in the beggining, it makes sense that AMD will want to be the only chipset supplier for a while. Until Clawhammer goes completely mainstream (momma, pop and sis buying one ), there's little sense on going integrated GPU. Of course, maketing could hype-up anything they want, but I don't see a market for different chipsets for the Hammer family at launch. >>


I agree that at launch you won't see integrated solutions (you almost never do) and I also agree that different types of chipsets won't be necessary at launch but in the end, AMD wants to sell CPUs and if having a VIA based Hammer chipset available at (or very close to) launch will help that then I can see it happening.


<< Can we say ... BitBoys Oy? >>


Yes we can

Take care,
Anand

 

[MadRat]

Hasn't AMD only said SLEDGE Hammer was for 1H03 and nothing about CLAW Hammer's release?

I'm not going to get excited about Claw Hammer until we see how its castrated compared to Sledge Hammer. All of the Hammer information these days is dwelling on its high end brethren and not so much on the lower end model.

 

[Utterman]

Err...I'm saving up to get a car in October. Guess it's going to come between getting a car or a really nice clawhammer and laptop system.

 

[Martin]

<< Hasn't AMD only said SLEDGE Hammer was for 1H03 and nothing about CLAW Hammer's release?

I'm not going to get excited about Claw Hammer until we see how its castrated compared to Sledge Hammer. All of the Hammer information these days is dwelling on its high end brethren and not so much on the lower end model. >>




There is quite a bit of info on Clawhammer as well.

Here are some details:
-256kb L2 cache
-103 mm^2 die
-67 million transistors
-.13u


As far as chipsets go, IMO, the launch will go like the 760, where AMD will be the sole supplier for a few months, while the other companies get their chipsets ready, after which AMD will pull out.


As for an October launch. I am skeptical, unless it is a Radeon 8500 type launch (which I doubt AMD will want to do). Before AMD can launch it, they'd have to get compilers, WindowsXP-64 (which was mentioned by Jerry Sanders, so its existent, but not official), as well as drivers etc.


But we'll see.



Btw, Anand, can you please upgrade the servers before the Hammer article? I remember having a hard time getting to last year's 760+DDR intro

 

[LukFilm]

<< << Can we say ... BitBoys Oy? >>

Yes we can >>



Does that mean that BitBoys Oy is a possible reality or a total joke? Not sure by the inference you made, Anand and I'd LOVE to know... Thanks.

 

[socketman]

We really should start a betting pool while its still early. Everyone cast their vote for which week Hammer will ship to OEMs. Then we lock the thread, and keep up top. When October arrives, we can jump for joy or hang our heads in shame...

I vote second week of October ( no reason, just sounds good)


I remember Intel was looking at SOI before P4 was taped out. I got the feeling they didnt think it offered a complete enough solution for what they wanted to do with Northwood. Someone posted a link a while back to streamcast lectures. Two of those lectures were from Intel CPU engineers. One of them talked about gate leakage, quantum tunneling, Dielectrics and stuff. He mentioned SOI, but didnt go into much detail. Which led me to think it wasnt a serious alternative for them.

 

[ElFenix]

intel doesn't need SOI yet, based on how their current processors are doing. the northwood is quite competitive from a actual performance standpoint, seems like it has lots of room from how well they overclock (and a few good steppings will increase that even more... intel got coppermine up to 1200), and is definitely winning the sheep war (where MHz is actual performance). SOI might be looked at later, but i have a feeling they'll complete that skeleton they have downtown here before we see SOI from them in a desktop chip. mckinley might have it, and i wouldn't know or care.


EDIT: i'll go with first week of november.


and remember when AMD was having trouble shipping 4 or 5 million k6s? they've come a long way since then, huh?

 

[formulav8]

I believe Intel only made it to 1ghz with the coppermine. They released a 1.13 ghz version but they recalled it.

 

[ST4RCUTTER]

Before AMD can launch it, they'd have to get compilers, WindowsXP-64 (which was mentioned by Jerry Sanders, so its existent, but not official), as well as drivers etc.


Why would this be necessary for a Hammer launch? The Hammer is a 32-bit chip with 64-bit extensions. AMD has already stated that the Clawhammer will be released to the desktop before we see the Sledgehammer. Does anyone know difinitively if the Hammer will have 512 or 256k of L2? It seems odd to me that AMD would bottleneck the improved memory performance of the MCT with only 256k of L2. Of course, with lowered latency more L2 may not even be necessary. I'm just wondering though... I keep seeing 512k from most of the hardware sites, but a few people are quoting 256. Does anyone know...cough cough...Anand...cough...which might be the correct number for Clawhammer.